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[mips] Teach the delay slot filler to remove needless KILL instructions.
Summary: Previously, the presence of KILL instructions would block valid candidates from filling a specific delay slot. With the elimination of the KILL instructions, in the appropriate range, we are able to fill more slots and keep the information from future def/use analysis consistent. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D7724 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235183 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -643,18 +643,34 @@ template<typename IterTy>
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bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
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IterTy &Filler) const {
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for (IterTy I = Begin; I != End; ++I) {
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bool IsReverseIter = std::is_convertible<IterTy, ReverseIter>::value;
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for (IterTy I = Begin; I != End;) {
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IterTy CurrI = I;
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++I;
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// skip debug value
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if (I->isDebugValue())
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if (CurrI->isDebugValue())
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continue;
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if (terminateSearch(*I))
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if (terminateSearch(*CurrI))
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break;
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assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
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assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
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"Cannot put calls, returns or branches in delay slot.");
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if (delayHasHazard(*I, RegDU, IM))
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if (CurrI->isKill()) {
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CurrI->eraseFromParent();
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// This special case is needed for reverse iterators, because when we
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// erase an instruction, the iterators are updated to point to the next
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// instruction.
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if (IsReverseIter && I != End)
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I = CurrI;
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continue;
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}
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if (delayHasHazard(*CurrI, RegDU, IM))
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continue;
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const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
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@ -664,21 +680,21 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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// branches are not checked because non-NaCl targets never put them in
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// delay slots.
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unsigned AddrIdx;
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if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) &&
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baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) ||
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I->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
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if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
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baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
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CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
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continue;
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}
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bool InMicroMipsMode = STI.inMicroMipsMode();
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const MipsInstrInfo *TII = STI.getInstrInfo();
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unsigned Opcode = (*Slot).getOpcode();
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if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*I)) == 2 &&
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if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*CurrI)) == 2 &&
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(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
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Opcode == Mips::PseudoReturn))
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continue;
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Filler = I;
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Filler = CurrI;
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return true;
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}
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@ -843,7 +859,10 @@ bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
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bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
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InspectMemInstr &IM) const {
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bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
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assert(!Candidate.isKill() &&
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"KILL instructions should have been eliminated at this point.");
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bool HasHazard = Candidate.isImplicitDef();
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HasHazard |= IM.hasHazard(Candidate);
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HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
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14
test/CodeGen/Mips/delay-slot-kill.ll
Normal file
14
test/CodeGen/Mips/delay-slot-kill.ll
Normal file
@ -0,0 +1,14 @@
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
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; Currently, the following IR assembly generates a KILL instruction between
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; the bitwise-and instruction and the return instruction. We verify that the
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; delay slot filler ignores such KILL instructions by filling the slot of the
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; return instruction properly.
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define signext i32 @f1(i32 signext %a, i32 signext %b) {
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entry:
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; CHECK: jr $ra
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; CHECK-NEXT: and $2, $4, $5
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%r = and i32 %a, %b
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ret i32 %r
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}
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