6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-26 05:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-05-11 17:00:48 +00:00
parent 1680832a9b
commit 18901d63bf
2 changed files with 10 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/ARM/ARMInstrThumb.td
View File

@@ -457,7 +457,11 @@ let isCall = 1,
"blx\t$func", "blx\t$func",
[(ARMtcall GPR:$func)]>, [(ARMtcall GPR:$func)]>,
Requires<[IsThumb, HasV5T, IsNotDarwin]>, Requires<[IsThumb, HasV5T, IsNotDarwin]>,
T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24; T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
bits<4> func;
let Inst{6-3} = func;
let Inst{2-0} = 0b000;
}
// ARMv4T // ARMv4T
// FIXME: Should be a pseudo. // FIXME: Should be a pseudo.
@@ -600,7 +604,7 @@ def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
// The assembler uses 0xDEFE for a trap instruction. // The assembler uses 0xDEFE for a trap instruction.
let isBarrier = 1, isTerminator = 1 in let isBarrier = 1, isTerminator = 1 in
def tTRAP : TI<(outs), (ins), IIC_Br, def tTRAP : TI<(outs), (ins), IIC_Br,
"trap", [(trap)]>, Encoding16 { "trap", [(trap)]>, Encoding16 {
let Inst = 0xdefe; let Inst = 0xdefe;
} }
@@ -807,7 +811,7 @@ defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
{1,1,0,0,0,?}, 0>; {1,1,0,0,0,?}, 0>;
} // neverHasSideEffects } // neverHasSideEffects
let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
@@ -1451,7 +1455,7 @@ def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SJLJ Exception handling intrinsics // SJLJ Exception handling intrinsics
// //
// eh_sjlj_setjmp() is an instruction sequence to store the return address and // eh_sjlj_setjmp() is an instruction sequence to store the return address and
// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming

2
test/MC/ARM/thumb.s
View File

@@ -12,6 +12,8 @@
@ CHECK: blx r9 @ encoding: [0xc8,0x47] @ CHECK: blx r9 @ encoding: [0xc8,0x47]
blx r9 blx r9
@ CHECK: blx r10 @ encoding: [0xd0,0x47]
blx r10
@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba] @ CHECK: rev r2, r3 @ encoding: [0x1a,0xba]
@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba] @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]