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[Hexagon] Adding add reg, imm form with encoding bits and test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223504 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -295,6 +295,85 @@ def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
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let Inst{4-0} = Rdd;
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}
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//===----------------------------------------------------------------------===//
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// Template class for predicated ADD of a reg and an Immediate value.
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1 in
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class T_Addri_Pred <bit PredNot, bit PredNew>
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: ALU32_ri <(outs IntRegs:$Rd),
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(ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
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!if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
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") $Rd = ")#"add($Rs, #$s8)"> {
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bits<5> Rd;
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bits<2> Pu;
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bits<5> Rs;
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bits<8> s8;
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let isPredicatedNew = PredNew;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0100;
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let Inst{23} = PredNot;
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let Inst{22-21} = Pu;
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let Inst{20-16} = Rs;
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let Inst{13} = PredNew;
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let Inst{12-5} = s8;
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let Inst{4-0} = Rd;
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}
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//===----------------------------------------------------------------------===//
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// A2_addi: Add a signed immediate to a register.
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1 in
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class T_Addri <Operand immOp, list<dag> pattern = [] >
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: ALU32_ri <(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, immOp:$s16),
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"$Rd = add($Rs, #$s16)", pattern,
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//[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
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"", ALU32_ADDI_tc_1_SLOT0123> {
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bits<5> Rd;
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bits<5> Rs;
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bits<16> s16;
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let IClass = 0b1011;
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let Inst{27-21} = s16{15-9};
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let Inst{20-16} = Rs;
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let Inst{13-5} = s16{8-0};
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let Inst{4-0} = Rd;
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}
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//===----------------------------------------------------------------------===//
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// Multiclass for ADD of a register and an immediate value.
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//===----------------------------------------------------------------------===//
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multiclass Addri_Pred<string mnemonic, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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def _c#NAME : T_Addri_Pred<PredNot, 0>;
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// Predicate new
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def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
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}
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}
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let isExtendable = 1, InputType = "imm" in
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multiclass Addri_base<string mnemonic, SDNode OpNode> {
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let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
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isPredicable = 1 in
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def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
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[(set (i32 IntRegs:$Rd),
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(add IntRegs:$Rs, s16ExtPred:$s16))]>;
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let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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hasSideEffects = 0, isPredicated = 1 in {
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defm Pt : Addri_Pred<mnemonic, 0>;
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defm NotPt : Addri_Pred<mnemonic, 1>;
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}
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}
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}
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let isCodeGenOnly = 0 in
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defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
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// Nop.
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let hasSideEffects = 0, isCodeGenOnly = 0 in
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def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
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@ -466,47 +545,6 @@ class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
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def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
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//===----------------------------------------------------------------------===//
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// ALU32/ALU (ADD with register-immediate form)
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//===----------------------------------------------------------------------===//
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multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
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") $dst = ")#mnemonic#"($src2, #$src3)",
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[]>;
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}
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multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
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}
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}
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let isExtendable = 1, InputType = "imm" in
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multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
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isPredicable = 1 in
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def NAME : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s16Ext:$src2),
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"$dst = "#mnemonic#"($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
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(s16ExtPred:$src2)))]>;
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let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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hasSideEffects = 0, isPredicated = 1 in {
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defm Pt : ALU32ri_Pred<mnemonic, 0>;
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defm NotPt : ALU32ri_Pred<mnemonic, 1>;
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}
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}
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}
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defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
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CextOpcode = "OR", InputType = "imm" in
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def OR_ri : ALU32_ri<(outs IntRegs:$dst),
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@ -1,5 +1,7 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0xf1 0xc3 0x15 0xb0
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# CHECK: r17 = add(r21, #31)
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0x11 0xdf 0x15 0xf3
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# CHECK: r17 = add(r21, r31)
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0x11 0xdf 0x15 0xf1
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