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Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
This reverts commit r191130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191138 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4327,27 +4327,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
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}
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}
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// Treat SETCC as a mask and promote the result type based on the targets
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// expected SETCC result type. This will ensure that SETCC and VSELECT are
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// both split by the type legalizer. This is done to prevent the type
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// legalizer from unrolling SETCC into scalar comparions.
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EVT SelectVT = N->getValueType(0);
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if (N0.getOpcode() == ISD::SETCC &&
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N0.getValueType() != getSetCCResultType(SelectVT)) {
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SDLoc MaskDL(N0);
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EVT MaskVT = getSetCCResultType(SelectVT);
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SDValue Mask = DAG.getNode(ISD::SETCC, MaskDL, MaskVT, N0->getOperand(0),
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N0->getOperand(1), N0->getOperand(2));
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AddToWorkList(Mask.getNode());
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS);
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}
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return SDValue();
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}
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@ -489,20 +489,14 @@ void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
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SDValue Cond = N->getOperand(0);
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CL = CH = Cond;
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if (Cond.getValueType().isVector()) {
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if (Cond.getOpcode() == ISD::SETCC) {
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assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) &&
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"Condition has not been prepared for split!");
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GetSplitVector(Cond, CL, CH);
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} else {
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assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
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"Condition legalized before result?");
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unsigned NumElements = Cond.getValueType().getVectorNumElements();
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EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
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CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
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DAG.getConstant(0, TLI.getVectorIdxTy()));
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CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
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DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
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}
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assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
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"Condition legalized before result?");
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unsigned NumElements = Cond.getValueType().getVectorNumElements();
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EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
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CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
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DAG.getConstant(0, TLI.getVectorIdxTy()));
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CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
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DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
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}
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Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
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@ -1535,16 +1535,7 @@ void X86TargetLowering::resetOperationActions() {
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}
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EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
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if (!VT.isVector())
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return MVT::i8;
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const TargetMachine &TM = getTargetMachine();
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if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
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switch(VT.getVectorNumElements()) {
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case 8: return MVT::v8i1;
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case 16: return MVT::v16i1;
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}
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if (!VT.isVector()) return MVT::i8;
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return VT.changeVectorElementTypeToInteger();
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}
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@ -1,38 +0,0 @@
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; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4
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; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
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; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
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define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {
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; SSE4-LABEL: split16:
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; SSE4: pminuw
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; SSE4: pminuw
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; AVX1-LABEL: split16:
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; AVX1: vpminuw
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; AVX1: vpminuw
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; AVX2-LABEL: split16:
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; AVX2: vpminuw
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; AVX2: ret
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%1 = icmp ult <16 x i16> %a, %b
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%2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
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ret <16 x i16> %2
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}
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define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {
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; SSE4-LABEL: split32:
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; SSE4: pminuw
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; SSE4: pminuw
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; SSE4: pminuw
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; SSE4: pminuw
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; AVX1-LABEL: split32:
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; AVX1: vpminuw
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; AVX1: vpminuw
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; AVX1: vpminuw
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; AVX1: vpminuw
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; AVX2-LABEL: split32:
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; AVX2: vpminuw
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; AVX2: vpminuw
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; AVX2: ret
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%1 = icmp ult <32 x i16> %a, %b
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%2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b
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ret <32 x i16> %2
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}
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