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LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.

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The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-03-09 20:01:14 +00:00
parent f607abdf7b
commit 18b475f954
2 changed files with 6 additions and 0 deletions
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3
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -94,6 +94,9 @@ static unsigned decodeARMInstruction(uint32_t &insn) {
// As a result, the decoder fails to deocode USAT properly. // As a result, the decoder fails to deocode USAT properly.
if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1) if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
return ARM::USAT; return ARM::USAT;
// As a result, the decoder fails to deocode UQADD16 properly.
if (slice(insn, 27, 20) == 0x66 && slice(insn, 7, 4) == 1)
return ARM::UQADD16;
// Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8. // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
// As a result, the decoder fails to decode UMULL properly. // As a result, the decoder fails to decode UMULL properly.

3
test/MC/Disassembler/ARM/arm-tests.txt
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@ -139,3 +139,6 @@
# CHECK: bx r12 # CHECK: bx r12
0x1c 0xff 0x2f 0xe1 0x1c 0xff 0x2f 0xe1
# CHECK: uqadd16mi r6, r11, r8
0x18 0x60 0x6b 0x46