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[Hexagon] Adding bit count and twiddling instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
50b3134fb4
commit
18f28b2de6
@ -2847,6 +2847,105 @@ def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
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//===----------------------------------------------------------------------===//
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// STYPE/BIT +
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//===----------------------------------------------------------------------===//
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// Bit count
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let hasSideEffects = 0, hasNewValue = 1 in
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class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
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dag Out, dag Inp>
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: SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
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bits<5> Rs;
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bits<5> Rd;
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let IClass = 0b1000;
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let Inst{27} = 0b1;
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let Inst{26} = Is32;
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let Inst{25-24} = 0b00;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rd;
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}
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class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
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: T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
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(outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
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class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
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: T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
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(outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
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let isCodeGenOnly = 0 in {
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def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
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def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
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def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
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def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
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def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
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def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
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def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
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def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
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def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
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}
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def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
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def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
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def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
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def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
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def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
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// Bit set/clear/toggle
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let hasSideEffects = 0, hasNewValue = 1 in
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class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
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: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
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"$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> u5;
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let IClass = 0b1000;
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let Inst{27-21} = 0b1100110;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b0;
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let Inst{12-8} = u5;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rd;
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}
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let hasSideEffects = 0, hasNewValue = 1 in
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class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
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: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-22} = 0b011010;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7-6} = MinOp;
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let Inst{4-0} = Rd;
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}
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let isCodeGenOnly = 0 in {
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def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
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def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
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def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
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def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
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def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
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def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
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}
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def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
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(S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
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def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
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(S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
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def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
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(S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
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def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
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(S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
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(S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
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(S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
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// clrbit.
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def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
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@ -1,8 +1,38 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x11 0xc0 0x54 0x88
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# CHECK: r17 = clb(r21:20)
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0x51 0xc0 0x54 0x88
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# CHECK: r17 = cl0(r21:20)
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0x91 0xc0 0x54 0x88
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# CHECK: r17 = cl1(r21:20)
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0x91 0xc0 0x15 0x8c
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# CHECK: r17 = clb(r21)
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0xb1 0xc0 0x15 0x8c
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# CHECK: r17 = cl0(r21)
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0xd1 0xc0 0x15 0x8c
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# CHECK: r17 = cl1(r21)
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0xf1 0xc0 0x15 0x8c
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# CHECK: r17 = normamt(r21)
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0x91 0xc0 0x55 0x8c
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# CHECK: r17 = ct0(r21)
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0xb1 0xc0 0x55 0x8c
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# CHECK: r17 = ct1(r21)
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0x90 0xc0 0xd4 0x80
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# CHECK: r17:16 = deinterleave(r21:20)
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0xb0 0xc0 0xd4 0x80
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# CHECK: r17:16 = interleave(r21:20)
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0x11 0xde 0x14 0xd0
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# CHECK: r17 = parity(r21:20, r31:30)
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0x11 0xdf 0xd5 0x8c
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# CHECK: r17 = setbit(r21, #31)
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0x31 0xdf 0xd5 0x8c
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# CHECK: r17 = clrbit(r21, #31)
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0x51 0xdf 0xd5 0x8c
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# CHECK: r17 = togglebit(r21, #31)
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0x11 0xdf 0x95 0xc6
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# CHECK: r17 = setbit(r21, r31)
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0x51 0xdf 0x95 0xc6
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# CHECK: r17 = clrbit(r21, r31)
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0x91 0xdf 0x95 0xc6
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# CHECK: r17 = togglebit(r21, r31)
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