From 19055cc2712223f6834fc3cf5b547803ba83f066 Mon Sep 17 00:00:00 2001 From: Matt Beaumont-Gay Date: Tue, 3 Jan 2012 19:03:59 +0000 Subject: [PATCH] Fix malformed assert. If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 705825478da..7e5e770a38b 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6192,7 +6192,7 @@ processInstruction(MCInst &Inst, ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); if (SOpc == ARM_AM::rrx) return false; switch (Inst.getOpcode()) { - default: assert("unexpected opcode!"); + default: assert(0 && "unexpected opcode!"); case ARM::ANDrsi: newOpc = ARM::ANDrr; break; case ARM::ORRrsi: newOpc = ARM::ORRrr; break; case ARM::EORrsi: newOpc = ARM::EORrr; break;