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introduce a isTypeInSSEReg predicate, which allows us to simplify

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some code.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-16 06:19:45 +00:00
parent 7ff79c2d9d
commit 1956d15676
2 changed files with 18 additions and 21 deletions
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32
lib/Target/X86/X86ISelLowering.cpp
View File

@ -760,8 +760,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
// If this is an FP return with ScalarSSE, we need to move the value from // If this is an FP return with ScalarSSE, we need to move the value from
// an XMM register onto the fp-stack. // an XMM register onto the fp-stack.
if ((X86ScalarSSEf32 && RVLocs[0].getValVT()==MVT::f32) || if (isTypeInSSEReg(RVLocs[0].getValVT())) {
(X86ScalarSSEf64 && RVLocs[0].getValVT()==MVT::f64)) {
SDOperand MemLoc; SDOperand MemLoc;
// If this is a load into a scalarsse value, don't store the loaded value // If this is a load into a scalarsse value, don't store the loaded value
@ -836,8 +835,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
// If we are using ScalarSSE, store ST(0) to the stack and reload it into // If we are using ScalarSSE, store ST(0) to the stack and reload it into
// an XMM register. // an XMM register.
if ((X86ScalarSSEf32 && RVLocs[0].getValVT() == MVT::f32) || if (isTypeInSSEReg(RVLocs[0].getValVT())) {
(X86ScalarSSEf64 && RVLocs[0].getValVT() == MVT::f64)) {
SDOperand StoreLoc; SDOperand StoreLoc;
const Value *SrcVal = 0; const Value *SrcVal = 0;
int SrcValOffset = 0; int SrcValOffset = 0;
@ -3862,18 +3860,15 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
StackSlot, NULL, 0); StackSlot, NULL, 0);
// These are really Legal; caller falls through into that case. // These are really Legal; caller falls through into that case.
if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f32 && X86ScalarSSEf32) if (SrcVT == MVT::i32 && isTypeInSSEReg(Op.getValueType()))
return Result; return Result;
if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f64 && X86ScalarSSEf64) if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
return Result;
if (SrcVT==MVT::i64 && Op.getValueType() != MVT::f80 &&
Subtarget->is64Bit()) Subtarget->is64Bit())
return Result; return Result;
// Build the FILD // Build the FILD
SDVTList Tys; SDVTList Tys;
bool useSSE = (X86ScalarSSEf32 && Op.getValueType() == MVT::f32) || bool useSSE = isTypeInSSEReg(Op.getValueType());
(X86ScalarSSEf64 && Op.getValueType() == MVT::f64);
if (useSSE) if (useSSE)
Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
else else
@ -3916,10 +3911,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
// These are really Legal. // These are really Legal.
if (Op.getValueType() == MVT::i32 && if (Op.getValueType() == MVT::i32 &&
X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) isTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDOperand(), SDOperand());
if (Op.getValueType() == MVT::i32 &&
X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)
return std::make_pair(SDOperand(), SDOperand()); return std::make_pair(SDOperand(), SDOperand());
if (Subtarget->is64Bit() && if (Subtarget->is64Bit() &&
Op.getValueType() == MVT::i64 && Op.getValueType() == MVT::i64 &&
@ -3942,8 +3934,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = DAG.getEntryNode(); SDOperand Chain = DAG.getEntryNode();
SDOperand Value = Op.getOperand(0); SDOperand Value = Op.getOperand(0);
if ((X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) || if (isTypeInSSEReg(Op.getOperand(0).getValueType())) {
(X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)) {
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
@ -4172,13 +4163,12 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
SDOperand Cmp = Cond.getOperand(1); SDOperand Cmp = Cond.getOperand(1);
unsigned Opc = Cmp.getOpcode(); unsigned Opc = Cmp.getOpcode();
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
bool IllegalFPCMov = false; bool IllegalFPCMov = false;
if (VT == MVT::f32 && !X86ScalarSSEf32) if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); !isTypeInSSEReg(VT)) // FPStack?
else if (VT == MVT::f64 && !X86ScalarSSEf64)
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
else if (VT == MVT::f80)
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
if ((Opc == X86ISD::CMP || if ((Opc == X86ISD::CMP ||
Opc == X86ISD::COMI || Opc == X86ISD::COMI ||
Opc == X86ISD::UCOMI) && !IllegalFPCMov) { Opc == X86ISD::UCOMI) && !IllegalFPCMov) {

7
lib/Target/X86/X86ISelLowering.h
View File

@ -425,6 +425,13 @@ namespace llvm {
/// When SSE2 is available, use it for f64 operations. /// When SSE2 is available, use it for f64 operations.
bool X86ScalarSSEf32; bool X86ScalarSSEf32;
bool X86ScalarSSEf64; bool X86ScalarSSEf64;
/// isTypeInSSEReg - Return true if the specified scalar FP type is computed
/// in an SSE register, not on the X87 floating point stack.
bool isTypeInSSEReg(MVT::ValueType VT) const {
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall, SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
unsigned CallingConv, SelectionDAG &DAG); unsigned CallingConv, SelectionDAG &DAG);