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introduce a isTypeInSSEReg predicate, which allows us to simplify
some code. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46055 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -760,8 +760,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
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// If this is an FP return with ScalarSSE, we need to move the value from
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// an XMM register onto the fp-stack.
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if ((X86ScalarSSEf32 && RVLocs[0].getValVT()==MVT::f32) ||
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(X86ScalarSSEf64 && RVLocs[0].getValVT()==MVT::f64)) {
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if (isTypeInSSEReg(RVLocs[0].getValVT())) {
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SDOperand MemLoc;
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// If this is a load into a scalarsse value, don't store the loaded value
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@ -836,8 +835,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
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// If we are using ScalarSSE, store ST(0) to the stack and reload it into
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// an XMM register.
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if ((X86ScalarSSEf32 && RVLocs[0].getValVT() == MVT::f32) ||
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(X86ScalarSSEf64 && RVLocs[0].getValVT() == MVT::f64)) {
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if (isTypeInSSEReg(RVLocs[0].getValVT())) {
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SDOperand StoreLoc;
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const Value *SrcVal = 0;
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int SrcValOffset = 0;
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@ -3862,9 +3860,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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StackSlot, NULL, 0);
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// These are really Legal; caller falls through into that case.
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if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f32 && X86ScalarSSEf32)
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return Result;
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if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f64 && X86ScalarSSEf64)
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if (SrcVT == MVT::i32 && isTypeInSSEReg(Op.getValueType()))
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return Result;
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if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
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Subtarget->is64Bit())
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@ -3872,8 +3868,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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// Build the FILD
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SDVTList Tys;
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bool useSSE = (X86ScalarSSEf32 && Op.getValueType() == MVT::f32) ||
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(X86ScalarSSEf64 && Op.getValueType() == MVT::f64);
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bool useSSE = isTypeInSSEReg(Op.getValueType());
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if (useSSE)
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Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
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else
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@ -3916,10 +3911,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
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// These are really Legal.
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if (Op.getValueType() == MVT::i32 &&
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X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32)
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return std::make_pair(SDOperand(), SDOperand());
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if (Op.getValueType() == MVT::i32 &&
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X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)
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isTypeInSSEReg(Op.getOperand(0).getValueType()))
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return std::make_pair(SDOperand(), SDOperand());
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if (Subtarget->is64Bit() &&
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Op.getValueType() == MVT::i64 &&
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@ -3942,8 +3934,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = DAG.getEntryNode();
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SDOperand Value = Op.getOperand(0);
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if ((X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) ||
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(X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)) {
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if (isTypeInSSEReg(Op.getOperand(0).getValueType())) {
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assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
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Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
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SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
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@ -4172,13 +4163,12 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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MVT::ValueType VT = Op.getValueType();
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bool IllegalFPCMov = false;
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if (VT == MVT::f32 && !X86ScalarSSEf32)
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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else if (VT == MVT::f64 && !X86ScalarSSEf64)
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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else if (VT == MVT::f80)
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if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
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!isTypeInSSEReg(VT)) // FPStack?
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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if ((Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
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@ -426,6 +426,13 @@ namespace llvm {
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bool X86ScalarSSEf32;
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bool X86ScalarSSEf64;
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/// isTypeInSSEReg - Return true if the specified scalar FP type is computed
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/// in an SSE register, not on the X87 floating point stack.
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bool isTypeInSSEReg(MVT::ValueType VT) const {
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return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
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(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
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}
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SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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