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Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-10-13 18:35:52 +00:00
parent bf8c4f2c6e
commit 195cd3a58d
2 changed files with 52 additions and 0 deletions
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10
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -460,6 +460,16 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
unsigned DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
DLR->valno->copy = NULL;
// Don't forget to update sub-register intervals.
if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
if (!li_->hasInterval(*SR))
continue;
DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
if (DLR && DLR->valno->copy == CopyMI)
DLR->valno->copy = NULL;
}
}
MachineBasicBlock::iterator MII = CopyMI;
MachineBasicBlock *MBB = CopyMI->getParent();

42
test/CodeGen/X86/2008-10-13-CoalescerBug.ll Normal file
View File

@ -0,0 +1,42 @@
; RUN: llvm-as < %s | llc -march=x86
; PR2775
define i32 @func_77(i8 zeroext %p_79) nounwind {
entry:
%0 = tail call i32 (...)* @func_43(i32 1) nounwind ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
br i1 %1, label %bb3, label %bb
bb: ; preds = %entry
br label %bb3
bb3: ; preds = %bb, %entry
%p_79_addr.0 = phi i8 [ 0, %bb ], [ %p_79, %entry ] ; <i8> [#uses=1]
%2 = zext i8 %p_79_addr.0 to i32 ; <i32> [#uses=2]
%3 = zext i1 false to i32 ; <i32> [#uses=2]
%4 = tail call i32 (...)* @rshift_u_s(i32 1) nounwind ; <i32> [#uses=0]
%5 = lshr i32 %2, %2 ; <i32> [#uses=3]
%6 = icmp eq i32 0, 0 ; <i1> [#uses=1]
br i1 %6, label %bb6, label %bb9
bb6: ; preds = %bb3
%7 = ashr i32 %5, %3 ; <i32> [#uses=1]
%8 = icmp eq i32 %7, 0 ; <i1> [#uses=1]
%9 = select i1 %8, i32 %3, i32 0 ; <i32> [#uses=1]
%. = shl i32 %5, %9 ; <i32> [#uses=1]
br label %bb9
bb9: ; preds = %bb6, %bb3
%.0 = phi i32 [ %., %bb6 ], [ %5, %bb3 ] ; <i32> [#uses=0]
br i1 false, label %return, label %bb10
bb10: ; preds = %bb9
ret i32 undef
return: ; preds = %bb9
ret i32 undef
}
declare i32 @func_43(...)
declare i32 @rshift_u_s(...)