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add FCPYS and FCPYD

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30995 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-10-17 13:13:23 +00:00
parent 5059dda6bd
commit 199dd67c50
2 changed files with 16 additions and 3 deletions
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5
lib/Target/ARM/ARMInstrInfo.td
View File

@ -212,6 +212,11 @@ def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
"fcmpd $a, $b",
[(armcmp DFPRegs:$a, DFPRegs:$b)]>;
// Floating Point Copy
def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
// Floating Point Conversion
// We use bitconvert for moving the data between the register classes.
// The format conversion is done with ARM specific nodes

14
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -47,9 +47,17 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
.addImm(ARMShift::LSL);
assert(RC == ARM::IntRegsRegisterClass ||
RC == ARM::FPRegsRegisterClass ||
RC == ARM::DFPRegsRegisterClass);
if (RC == ARM::IntRegsRegisterClass)
BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
.addImm(ARMShift::LSL);
else if (RC == ARM::FPRegsRegisterClass)
BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
else
BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,