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[ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
2014-03-20 05:36:59 +00:00
parent 0a70f9b3b9
commit 19a3e9aabe
2 changed files with 68 additions and 3 deletions
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12
lib/Target/ARM/A15SDOptimizer.cpp
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@@ -416,7 +416,8 @@ SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
if (!MO.isReg() || !MO.isUse())
continue;
if (!usesRegClass(MO, &ARM::DPRRegClass) &&
!usesRegClass(MO, &ARM::QPRRegClass))
!usesRegClass(MO, &ARM::QPRRegClass) &&
!usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
continue;
Defs.push_back(MO.getReg());
@@ -536,7 +537,10 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
InsertPt++;
unsigned Out;
if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
// DPair has the same length as QPR and also has two DPRs as subreg.
// Treat DPair as QPR.
if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
ARM::dsub_0, &ARM::DPRRegClass);
unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
@@ -569,7 +573,9 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
default: llvm_unreachable("Unknown preferred lane!");
}
bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
// Treat DPair as QPR
bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
Out = createImplicitDef(MBB, InsertPt, DL);
Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);