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https://github.com/c64scene-ar/llvm-6502.git
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Untabify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62991 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel
parent
c9c8b2a804
commit
19c10e658a
@ -633,9 +633,9 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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} else {
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/* If otherwise unadorned, default to D-form address with 0 offset: */
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if (Opc == ISD::CopyFromReg) {
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Index = N.getOperand(1);
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Index = N.getOperand(1);
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} else {
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Index = N;
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Index = N;
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}
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Base = CurDAG->getTargetConstant(0, Index.getValueType());
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@ -608,7 +608,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// specified by the operand:
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MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
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result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT,
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DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
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DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
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// Handle extending loads by extending the scalar result:
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if (ExtType == ISD::SEXTLOAD) {
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@ -619,7 +619,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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unsigned NewOpc = ISD::ANY_EXTEND;
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if (OutVT.isFloatingPoint())
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NewOpc = ISD::FP_EXTEND;
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NewOpc = ISD::FP_EXTEND;
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result = DAG.getNode(NewOpc, OutVT, result);
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}
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@ -775,8 +775,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue);
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result = DAG.getNode(SPUISD::SHUFB, vecVT,
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vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
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vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
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result = DAG.getStore(the_chain, result, basePtr,
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LN->getSrcValue(), LN->getSrcValueOffset(),
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@ -2094,7 +2094,7 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(SPUISD::SHUFB, VT,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
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VecOp,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
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return result;
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}
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@ -28,8 +28,8 @@ namespace {
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unsigned opc = I->getOpcode();
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return (opc == SPU::BR
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|| opc == SPU::BRA
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|| opc == SPU::BI);
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|| opc == SPU::BRA
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|| opc == SPU::BI);
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}
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//! Predicate for a conditional branch instruction
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@ -38,12 +38,12 @@ namespace {
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return (opc == SPU::BRNZr32
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|| opc == SPU::BRNZv4i32
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|| opc == SPU::BRZr32
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|| opc == SPU::BRZv4i32
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|| opc == SPU::BRHNZr16
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|| opc == SPU::BRHNZv8i16
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|| opc == SPU::BRHZr16
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|| opc == SPU::BRHZv8i16);
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|| opc == SPU::BRZr32
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|| opc == SPU::BRZv4i32
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|| opc == SPU::BRHNZr16
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|| opc == SPU::BRHNZv8i16
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|| opc == SPU::BRHZr16
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|| opc == SPU::BRHZv8i16);
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}
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}
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@ -531,8 +531,8 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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*/
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bool
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SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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@ -621,8 +621,8 @@ SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned
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SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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@ -103,14 +103,14 @@ namespace llvm {
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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};
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}
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@ -624,25 +624,25 @@ defm A : AddInstruction;
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class AIInst<dag OOL, dag IOL, list<dag> pattern>:
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RI10Form<0b00111000, OOL, IOL,
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"ai\t$rT, $rA, $val", IntegerOp,
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pattern>;
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"ai\t$rT, $rA, $val", IntegerOp,
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pattern>;
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class AIVecInst<ValueType vectype, PatLeaf immpred>:
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AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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[(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
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[(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
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class AIFPVecInst<ValueType vectype, PatLeaf immpred>:
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AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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[/* no pattern */]>;
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[/* no pattern */]>;
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class AIRegInst<RegisterClass rclass, PatLeaf immpred>:
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AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
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[(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
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[(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
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// This is used to add epsilons to floating point numbers in the f32 fdiv code:
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class AIFPInst<RegisterClass rclass, PatLeaf immpred>:
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AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
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[/* no pattern */]>;
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[/* no pattern */]>;
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multiclass AddImmediate {
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def v4i32: AIVecInst<v4i32, v4i32SExt10Imm>;
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@ -1969,11 +1969,11 @@ multiclass SelectBits
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def v2i64_vcond: SELBVecCondInst<v2i64>;
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def v4f32_cond:
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SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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[(set (v4f32 VECREG:$rT),
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(select (v4i32 VECREG:$rC),
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(v4f32 VECREG:$rB),
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(v4f32 VECREG:$rA)))]>;
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SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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[(set (v4f32 VECREG:$rT),
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(select (v4i32 VECREG:$rC),
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(v4f32 VECREG:$rB),
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(v4f32 VECREG:$rA)))]>;
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// SELBr64_cond is defined in SPU64InstrInfo.td
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def r32_cond: SELBRegCondInst<R32C, R32C>;
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@ -3260,7 +3260,7 @@ multiclass CmpGtrWordImm
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(v4i32 v4i32SExt16Imm:$val)))]>;
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def f32: CGTIInst<(outs R32C:$rT), (ins R32FP:$rA, s10imm_i32:$val),
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[/* no pattern */]>;
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[/* no pattern */]>;
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}
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class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
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@ -66,15 +66,15 @@ def Interpf32: CodeFrag<(FIf32 R32FP:$rB, (FRESTf32 R32FP:$rB))>;
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def DivEstf32: CodeFrag<(FMf32 R32FP:$rA, Interpf32.Fragment)>;
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// Newton-Raphson iteration
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def NRaphf32: CodeFrag<(FMAf32 (FNMSf32 DivEstf32.Fragment, R32FP:$rB, R32FP:$rA),
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Interpf32.Fragment,
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DivEstf32.Fragment)>;
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Interpf32.Fragment,
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DivEstf32.Fragment)>;
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// Epsilon addition
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def Epsilonf32: CodeFrag<(AIf32 NRaphf32.Fragment, 1)>;
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def : Pat<(fdiv R32FP:$rA, R32FP:$rB),
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(SELBf32_cond NRaphf32.Fragment,
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Epsilonf32.Fragment,
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(CGTIf32 (FNMSf32 R32FP:$rB, Epsilonf32.Fragment, R32FP:$rA), -1))>;
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(SELBf32_cond NRaphf32.Fragment,
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Epsilonf32.Fragment,
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(CGTIf32 (FNMSf32 R32FP:$rB, Epsilonf32.Fragment, R32FP:$rA), -1))>;
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// Reciprocal estimate and interpolation
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def Interpv4f32: CodeFrag<(FIv4f32 (v4f32 VECREG:$rB), (FRESTv4f32 (v4f32 VECREG:$rB)))>;
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@ -82,16 +82,16 @@ def Interpv4f32: CodeFrag<(FIv4f32 (v4f32 VECREG:$rB), (FRESTv4f32 (v4f32 VECREG
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def DivEstv4f32: CodeFrag<(FMv4f32 (v4f32 VECREG:$rA), Interpv4f32.Fragment)>;
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// Newton-Raphson iteration
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def NRaphv4f32: CodeFrag<(FMAv4f32 (FNMSv4f32 DivEstv4f32.Fragment,
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(v4f32 VECREG:$rB),
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(v4f32 VECREG:$rA)),
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Interpv4f32.Fragment,
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DivEstv4f32.Fragment)>;
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(v4f32 VECREG:$rB),
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(v4f32 VECREG:$rA)),
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Interpv4f32.Fragment,
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DivEstv4f32.Fragment)>;
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// Epsilon addition
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def Epsilonv4f32: CodeFrag<(AIv4f32 NRaphv4f32.Fragment, 1)>;
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def : Pat<(fdiv (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
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(SELBv4f32_cond NRaphv4f32.Fragment,
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Epsilonv4f32.Fragment,
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(CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
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Epsilonv4f32.Fragment,
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(v4f32 VECREG:$rA)), -1))>;
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(SELBv4f32_cond NRaphv4f32.Fragment,
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Epsilonv4f32.Fragment,
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(CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
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Epsilonv4f32.Fragment,
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(v4f32 VECREG:$rA)), -1))>;
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