From 19c5c4cca9edd0e1e2961879d3da164325af6d63 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 31 Jan 2006 05:04:52 +0000 Subject: [PATCH] Only insert an AND when converting from BR_COND to BRCC if needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25832 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 79037d3020f..f09fa625006 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -703,7 +703,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } else { // Make sure the condition is either zero or one. It may have been // promoted from something else. - Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); + unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); + if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) + Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,