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1) Improve comments.
2) Don't try to insert an i64 value into the low part of a vector with movq on an x86-32 target. This allows us to compile: __m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);} into: _doload64: movaps LCPI1_0, %xmm0 ret instead of: _doload64: subl $28, %esp movl $0, 4(%esp) movl $1, (%esp) movq (%esp), %xmm0 addl $28, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48057 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3055,7 +3055,15 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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if (NumNonZero == 1 && NumElems <= 4) {
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unsigned Idx = CountTrailingZeros_32(NonZeros);
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SDOperand Item = Op.getOperand(Idx);
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if (Idx == 0) {
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// If we have a constant or non-constant insertion into the low element of
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// a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
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// the rest of the elements. This will be matched as movd/movq/movss/movsd
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// depending on what the source datatype is. Because we can only get here
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// when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
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if (Idx == 0 &&
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// Don't do this for i64 values on x86-32.
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(EVT != MVT::i64 || Subtarget->is64Bit())) {
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
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// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
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return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
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@ -3065,6 +3073,11 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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if (IsAllConstants) // Otherwise, it's better to do a constpool load.
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return SDOperand();
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// Otherwise, if this is a vector with i32 or f32 elements, and the element
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// is a non-constant being inserted into an element other than the low one,
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// we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
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// movd/movss) to move this into the low element, then shuffle it into
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// place.
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if (EVTBits == 32) {
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
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