mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-05 13:26:55 +00:00
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
@@ -694,3 +694,398 @@
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0x20 0xa4 0x13 0x4f
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0x20 0xa4 0x13 0x2f
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0x20 0xa4 0x0b 0x6f
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#-----------------------------------------------------------------------------
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#Integer shift right (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: sshr v0.8b, v1.8b, #3
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# CHECK: sshr v0.4h, v1.4h, #3
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# CHECK: sshr v0.2s, v1.2s, #3
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# CHECK: sshr v0.16b, v1.16b, #3
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# CHECK: sshr v0.8h, v1.8h, #3
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# CHECK: sshr v0.4s, v1.4s, #3
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# CHECK: sshr v0.2d, v1.2d, #3
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0x20,0x04,0x0d,0x0f
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0x20,0x04,0x1d,0x0f
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0x20,0x04,0x3d,0x0f
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0x20,0x04,0x0d,0x4f
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0x20,0x04,0x1d,0x4f
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0x20,0x04,0x3d,0x4f
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0x20,0x04,0x7d,0x4f
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#-----------------------------------------------------------------------------
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#Integer shift right (Unsigned)
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#-----------------------------------------------------------------------------
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# CHECK: ushr v0.8b, v1.8b, #3
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# CHECK: ushr v0.4h, v1.4h, #3
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# CHECK: ushr v0.2s, v1.2s, #3
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# CHECK: ushr v0.16b, v1.16b, #3
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# CHECK: ushr v0.8h, v1.8h, #3
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# CHECK: ushr v0.4s, v1.4s, #3
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# CHECK: ushr v0.2d, v1.2d, #3
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0x20,0x04,0x0d,0x2f
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0x20,0x04,0x1d,0x2f
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0x20,0x04,0x3d,0x2f
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0x20,0x04,0x0d,0x6f
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0x20,0x04,0x1d,0x6f
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0x20,0x04,0x3d,0x6f
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0x20,0x04,0x7d,0x6f
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#-----------------------------------------------------------------------------
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#Integer shift right and accumulate (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: ssra v0.8b, v1.8b, #3
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# CHECK: ssra v0.4h, v1.4h, #3
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# CHECK: ssra v0.2s, v1.2s, #3
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# CHECK: ssra v0.16b, v1.16b, #3
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# CHECK: ssra v0.8h, v1.8h, #3
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# CHECK: ssra v0.4s, v1.4s, #3
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# CHECK: ssra v0.2d, v1.2d, #3
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0x20,0x14,0x0d,0x0f
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0x20,0x14,0x1d,0x0f
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0x20,0x14,0x3d,0x0f
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0x20,0x14,0x0d,0x4f
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0x20,0x14,0x1d,0x4f
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0x20,0x14,0x3d,0x4f
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0x20,0x14,0x7d,0x4f
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#-----------------------------------------------------------------------------
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#Integer shift right and accumulate (Unsigned)
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#-----------------------------------------------------------------------------
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# CHECK: usra v0.8b, v1.8b, #3
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# CHECK: usra v0.4h, v1.4h, #3
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# CHECK: usra v0.2s, v1.2s, #3
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# CHECK: usra v0.16b, v1.16b, #3
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# CHECK: usra v0.8h, v1.8h, #3
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# CHECK: usra v0.4s, v1.4s, #3
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# CHECK: usra v0.2d, v1.2d, #3
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0x20,0x14,0x0d,0x2f
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0x20,0x14,0x1d,0x2f
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0x20,0x14,0x3d,0x2f
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0x20,0x14,0x0d,0x6f
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0x20,0x14,0x1d,0x6f
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0x20,0x14,0x3d,0x6f
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0x20,0x14,0x7d,0x6f
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#-----------------------------------------------------------------------------
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#Integer rounding shift right (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: srshr v0.8b, v1.8b, #3
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# CHECK: srshr v0.4h, v1.4h, #3
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# CHECK: srshr v0.2s, v1.2s, #3
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# CHECK: srshr v0.16b, v1.16b, #3
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# CHECK: srshr v0.8h, v1.8h, #3
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# CHECK: srshr v0.4s, v1.4s, #3
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# CHECK: srshr v0.2d, v1.2d, #3
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0x20,0x24,0x0d,0x0f
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0x20,0x24,0x1d,0x0f
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0x20,0x24,0x3d,0x0f
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0x20,0x24,0x0d,0x4f
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0x20,0x24,0x1d,0x4f
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0x20,0x24,0x3d,0x4f
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0x20,0x24,0x7d,0x4f
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#-----------------------------------------------------------------------------
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#Integer rounding shift right (Unsigned)
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#-----------------------------------------------------------------------------
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# CHECK: urshr v0.8b, v1.8b, #3
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# CHECK: urshr v0.4h, v1.4h, #3
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# CHECK: urshr v0.2s, v1.2s, #3
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# CHECK: urshr v0.16b, v1.16b, #3
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# CHECK: urshr v0.8h, v1.8h, #3
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# CHECK: urshr v0.4s, v1.4s, #3
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# CHECK: urshr v0.2d, v1.2d, #3
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0x20,0x24,0x0d,0x2f
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0x20,0x24,0x1d,0x2f
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0x20,0x24,0x3d,0x2f
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0x20,0x24,0x0d,0x6f
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0x20,0x24,0x1d,0x6f
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0x20,0x24,0x3d,0x6f
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0x20,0x24,0x7d,0x6f
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#-----------------------------------------------------------------------------
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#Integer rounding shift right and accumulate (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: srsra v0.8b, v1.8b, #3
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# CHECK: srsra v0.4h, v1.4h, #3
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# CHECK: srsra v0.2s, v1.2s, #3
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# CHECK: srsra v0.16b, v1.16b, #3
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# CHECK: srsra v0.8h, v1.8h, #3
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# CHECK: srsra v0.4s, v1.4s, #3
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# CHECK: srsra v0.2d, v1.2d, #3
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0x20,0x34,0x0d,0x0f
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0x20,0x34,0x1d,0x0f
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0x20,0x34,0x3d,0x0f
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0x20,0x34,0x0d,0x4f
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0x20,0x34,0x1d,0x4f
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0x20,0x34,0x3d,0x4f
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0x20,0x34,0x7d,0x4f
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#-----------------------------------------------------------------------------
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#Integer rounding shift right and accumulate (Unsigned)
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#-----------------------------------------------------------------------------
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# CHECK: ursra v0.8b, v1.8b, #3
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# CHECK: ursra v0.4h, v1.4h, #3
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# CHECK: ursra v0.2s, v1.2s, #3
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# CHECK: ursra v0.16b, v1.16b, #3
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# CHECK: ursra v0.8h, v1.8h, #3
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# CHECK: ursra v0.4s, v1.4s, #3
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# CHECK: ursra v0.2d, v1.2d, #3
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0x20,0x34,0x0d,0x2f
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0x20,0x34,0x1d,0x2f
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0x20,0x34,0x3d,0x2f
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0x20,0x34,0x0d,0x6f
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0x20,0x34,0x1d,0x6f
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0x20,0x34,0x3d,0x6f
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0x20,0x34,0x7d,0x6f
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#-----------------------------------------------------------------------------
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#Integer shift right and insert
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#-----------------------------------------------------------------------------
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# CHECK: sri v0.8b, v1.8b, #3
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# CHECK: sri v0.4h, v1.4h, #3
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# CHECK: sri v0.2s, v1.2s, #3
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# CHECK: sri v0.16b, v1.16b, #3
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# CHECK: sri v0.8h, v1.8h, #3
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# CHECK: sri v0.4s, v1.4s, #3
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# CHECK: sri v0.2d, v1.2d, #3
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0x20,0x44,0x0d,0x2f
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0x20,0x44,0x1d,0x2f
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0x20,0x44,0x3d,0x2f
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0x20,0x44,0x0d,0x6f
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0x20,0x44,0x1d,0x6f
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0x20,0x44,0x3d,0x6f
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0x20,0x44,0x7d,0x6f
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#-----------------------------------------------------------------------------
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#Integer shift left and insert
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#-----------------------------------------------------------------------------
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# CHECK: sli v0.8b, v1.8b, #3
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# CHECK: sli v0.4h, v1.4h, #3
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# CHECK: sli v0.2s, v1.2s, #3
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# CHECK: sli v0.16b, v1.16b, #3
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# CHECK: sli v0.8h, v1.8h, #3
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# CHECK: sli v0.4s, v1.4s, #3
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# CHECK: sli v0.2d, v1.2d, #3
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0x20,0x54,0x0b,0x2f
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0x20,0x54,0x13,0x2f
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0x20,0x54,0x23,0x2f
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0x20,0x54,0x0b,0x6f
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0x20,0x54,0x13,0x6f
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0x20,0x54,0x23,0x6f
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0x20,0x54,0x43,0x6f
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#-----------------------------------------------------------------------------
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#Integer saturating shift left unsigned
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#-----------------------------------------------------------------------------
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# CHECK: sqshlu v0.8b, v1.8b, #3
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# CHECK: sqshlu v0.4h, v1.4h, #3
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# CHECK: sqshlu v0.2s, v1.2s, #3
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# CHECK: sqshlu v0.16b, v1.16b, #3
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# CHECK: sqshlu v0.8h, v1.8h, #3
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# CHECK: sqshlu v0.4s, v1.4s, #3
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# CHECK: sqshlu v0.2d, v1.2d, #3
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0x20,0x64,0x0b,0x2f
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0x20,0x64,0x13,0x2f
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0x20,0x64,0x23,0x2f
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0x20,0x64,0x0b,0x6f
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0x20,0x64,0x13,0x6f
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0x20,0x64,0x23,0x6f
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0x20,0x64,0x43,0x6f
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#-----------------------------------------------------------------------------
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#Integer saturating shift left (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: sqshl v0.8b, v1.8b, #3
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# CHECK: sqshl v0.4h, v1.4h, #3
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# CHECK: sqshl v0.2s, v1.2s, #3
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# CHECK: sqshl v0.16b, v1.16b, #3
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# CHECK: sqshl v0.8h, v1.8h, #3
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# CHECK: sqshl v0.4s, v1.4s, #3
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# CHECK: sqshl v0.2d, v1.2d, #3
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0x20,0x74,0x0b,0x0f
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0x20,0x74,0x13,0x0f
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0x20,0x74,0x23,0x0f
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0x20,0x74,0x0b,0x4f
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0x20,0x74,0x13,0x4f
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0x20,0x74,0x23,0x4f
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0x20,0x74,0x43,0x4f
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#-----------------------------------------------------------------------------
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#Integer saturating shift left (Unsigned)
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#-----------------------------------------------------------------------------
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# CHECK: uqshl v0.8b, v1.8b, #3
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# CHECK: uqshl v0.4h, v1.4h, #3
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# CHECK: uqshl v0.2s, v1.2s, #3
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# CHECK: uqshl v0.16b, v1.16b, #3
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# CHECK: uqshl v0.8h, v1.8h, #3
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# CHECK: uqshl v0.4s, v1.4s, #3
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# CHECK: uqshl v0.2d, v1.2d, #3
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0x20,0x74,0x0b,0x2f
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0x20,0x74,0x13,0x2f
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0x20,0x74,0x23,0x2f
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0x20,0x74,0x0b,0x6f
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0x20,0x74,0x13,0x6f
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0x20,0x74,0x23,0x6f
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0x20,0x74,0x43,0x6f
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#-----------------------------------------------------------------------------
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#Integer shift right narrow
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#-----------------------------------------------------------------------------
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# CHECK: shrn v0.8b, v1.8h, #3
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# CHECK: shrn v0.4h, v1.4s, #3
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# CHECK: shrn v0.2s, v1.2d, #3
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# CHECK: shrn2 v0.16b, v1.8h, #3
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# CHECK: shrn2 v0.8h, v1.4s, #3
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# CHECK: shrn2 v0.4s, v1.2d, #3
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0x20,0x84,0x0d,0x0f
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0x20,0x84,0x1d,0x0f
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0x20,0x84,0x3d,0x0f
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0x20,0x84,0x0d,0x4f
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0x20,0x84,0x1d,0x4f
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0x20,0x84,0x3d,0x4f
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#-----------------------------------------------------------------------------
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#Integer saturating shift right unsigned narrow (Signed)
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#-----------------------------------------------------------------------------
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# CHECK: sqshrun v0.8b, v1.8h, #3
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# CHECK: sqshrun v0.4h, v1.4s, #3
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# CHECK: sqshrun v0.2s, v1.2d, #3
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# CHECK: sqshrun2 v0.16b, v1.8h, #3
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# CHECK: sqshrun2 v0.8h, v1.4s, #3
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# CHECK: sqshrun2 v0.4s, v1.2d, #3
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0x20,0x84,0x0d,0x2f
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0x20,0x84,0x1d,0x2f
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0x20,0x84,0x3d,0x2f
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0x20,0x84,0x0d,0x6f
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0x20,0x84,0x1d,0x6f
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0x20,0x84,0x3d,0x6f
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#-----------------------------------------------------------------------------
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#Integer rounding shift right narrow
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#-----------------------------------------------------------------------------
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# CHECK: rshrn v0.8b, v1.8h, #3
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# CHECK: rshrn v0.4h, v1.4s, #3
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# CHECK: rshrn v0.2s, v1.2d, #3
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# CHECK: rshrn2 v0.16b, v1.8h, #3
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# CHECK: rshrn2 v0.8h, v1.4s, #3
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# CHECK: rshrn2 v0.4s, v1.2d, #3
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0x20,0x8c,0x0d,0x0f
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0x20,0x8c,0x1d,0x0f
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||||
0x20,0x8c,0x3d,0x0f
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||||
0x20,0x8c,0x0d,0x4f
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||||
0x20,0x8c,0x1d,0x4f
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||||
0x20,0x8c,0x3d,0x4f
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||||
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#-----------------------------------------------------------------------------
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#Integer saturating shift right rounded unsigned narrow (Signed)
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||||
#-----------------------------------------------------------------------------
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# CHECK: sqrshrun v0.8b, v1.8h, #3
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# CHECK: sqrshrun v0.4h, v1.4s, #3
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||||
# CHECK: sqrshrun v0.2s, v1.2d, #3
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||||
# CHECK: sqrshrun2 v0.16b, v1.8h, #3
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||||
# CHECK: sqrshrun2 v0.8h, v1.4s, #3
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||||
# CHECK: sqrshrun2 v0.4s, v1.2d, #3
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||||
0x20,0x8c,0x0d,0x2f
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||||
0x20,0x8c,0x1d,0x2f
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||||
0x20,0x8c,0x3d,0x2f
|
||||
0x20,0x8c,0x0d,0x6f
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||||
0x20,0x8c,0x1d,0x6f
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||||
0x20,0x8c,0x3d,0x6f
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||||
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#-----------------------------------------------------------------------------
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#Integer saturating shift right narrow (Signed)
|
||||
#-----------------------------------------------------------------------------
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||||
# CHECK: sqshrn v0.8b, v1.8h, #3
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||||
# CHECK: sqshrn v0.4h, v1.4s, #3
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# CHECK: sqshrn v0.2s, v1.2d, #3
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# CHECK: sqshrn2 v0.16b, v1.8h, #3
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# CHECK: sqshrn2 v0.8h, v1.4s, #3
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||||
# CHECK: sqshrn2 v0.4s, v1.2d, #3
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||||
0x20,0x94,0x0d,0x0f
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||||
0x20,0x94,0x1d,0x0f
|
||||
0x20,0x94,0x3d,0x0f
|
||||
0x20,0x94,0x0d,0x4f
|
||||
0x20,0x94,0x1d,0x4f
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||||
0x20,0x94,0x3d,0x4f
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||||
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#-----------------------------------------------------------------------------
|
||||
#Integer saturating shift right narrow (Unsigned)
|
||||
#-----------------------------------------------------------------------------
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||||
# CHECK: uqshrn v0.8b, v1.8h, #3
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||||
# CHECK: uqshrn v0.4h, v1.4s, #3
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||||
# CHECK: uqshrn v0.2s, v1.2d, #3
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||||
# CHECK: uqshrn2 v0.16b, v1.8h, #3
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||||
# CHECK: uqshrn2 v0.8h, v1.4s, #3
|
||||
# CHECK: uqshrn2 v0.4s, v1.2d, #3
|
||||
0x20,0x94,0x0d,0x2f
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||||
0x20,0x94,0x1d,0x2f
|
||||
0x20,0x94,0x3d,0x2f
|
||||
0x20,0x94,0x0d,0x6f
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0x20,0x94,0x1d,0x6f
|
||||
0x20,0x94,0x3d,0x6f
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
#Integer saturating shift right rounded narrow (Signed)
|
||||
#-----------------------------------------------------------------------------
|
||||
# CHECK: sqrshrn v0.8b, v1.8h, #3
|
||||
# CHECK: sqrshrn v0.4h, v1.4s, #3
|
||||
# CHECK: sqrshrn v0.2s, v1.2d, #3
|
||||
# CHECK: sqrshrn2 v0.16b, v1.8h, #3
|
||||
# CHECK: sqrshrn2 v0.8h, v1.4s, #3
|
||||
# CHECK: sqrshrn2 v0.4s, v1.2d, #3
|
||||
0x20,0x9c,0x0d,0x0f
|
||||
0x20,0x9c,0x1d,0x0f
|
||||
0x20,0x9c,0x3d,0x0f
|
||||
0x20,0x9c,0x0d,0x4f
|
||||
0x20,0x9c,0x1d,0x4f
|
||||
0x20,0x9c,0x3d,0x4f
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
#Integer saturating shift right rounded narrow (Unsigned)
|
||||
#-----------------------------------------------------------------------------
|
||||
# CHECK: uqrshrn v0.8b, v1.8h, #3
|
||||
# CHECK: uqrshrn v0.4h, v1.4s, #3
|
||||
# CHECK: uqrshrn v0.2s, v1.2d, #3
|
||||
# CHECK: uqrshrn2 v0.16b, v1.8h, #3
|
||||
# CHECK: uqrshrn2 v0.8h, v1.4s, #3
|
||||
# CHECK: uqrshrn2 v0.4s, v1.2d, #3
|
||||
0x20,0x9c,0x0d,0x2f
|
||||
0x20,0x9c,0x1d,0x2f
|
||||
0x20,0x9c,0x3d,0x2f
|
||||
0x20,0x9c,0x0d,0x6f
|
||||
0x20,0x9c,0x1d,0x6f
|
||||
0x20,0x9c,0x3d,0x6f
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
#Fixed-point convert to floating-point
|
||||
#-----------------------------------------------------------------------------
|
||||
# CHECK: scvtf v0.2s, v1.2s, #3
|
||||
# CHECK: scvtf v0.4s, v1.4s, #3
|
||||
# CHECK: scvtf v0.2d, v1.2d, #3
|
||||
# CHECK: ucvtf v0.2s, v1.2s, #3
|
||||
# CHECK: ucvtf v0.4s, v1.4s, #3
|
||||
# CHECK: ucvtf v0.2d, v1.2d, #3
|
||||
|
||||
0x20,0xe4,0x3d,0x0f
|
||||
0x20,0xe4,0x3d,0x4f
|
||||
0x20,0xe4,0x7d,0x4f
|
||||
0x20,0xe4,0x3d,0x2f
|
||||
0x20,0xe4,0x3d,0x6f
|
||||
0x20,0xe4,0x7d,0x6f
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
#Floating-point convert to fixed-point
|
||||
#-----------------------------------------------------------------------------
|
||||
# CHECK: fcvtzs v0.2s, v1.2s, #3
|
||||
# CHECK: fcvtzs v0.4s, v1.4s, #3
|
||||
# CHECK: fcvtzs v0.2d, v1.2d, #3
|
||||
# CHECK: fcvtzu v0.2s, v1.2s, #3
|
||||
# CHECK: fcvtzu v0.4s, v1.4s, #3
|
||||
# CHECK: fcvtzu v0.2d, v1.2d, #3
|
||||
0x20,0xfc,0x3d,0x0f
|
||||
0x20,0xfc,0x3d,0x4f
|
||||
0x20,0xfc,0x7d,0x4f
|
||||
0x20,0xfc,0x3d,0x2f
|
||||
0x20,0xfc,0x3d,0x6f
|
||||
0x20,0xfc,0x7d,0x6f
|
||||
|
||||
Reference in New Issue
Block a user