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Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting

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with the real FLT_ROUNDS (defined in <float.h>).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-01-31 00:41:03 +00:00
parent 00dff8dda2
commit 1a0248690a
7 changed files with 12 additions and 12 deletions
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4
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -404,13 +404,13 @@ namespace ISD {
/// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
FP_ROUND, FP_ROUND,
// FLT_ROUNDS - Returns current rounding mode: // FLT_ROUNDS_ - Returns current rounding mode:
// -1 Undefined // -1 Undefined
// 0 Round to 0 // 0 Round to 0
// 1 Round to nearest // 1 Round to nearest
// 2 Round to +inf // 2 Round to +inf
// 3 Round to -inf // 3 Round to -inf
FLT_ROUNDS, FLT_ROUNDS_,
/// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
/// rounds it to a floating point value. It then promotes it and returns it /// rounds it to a floating point value. It then promotes it and returns it

2
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3902,7 +3902,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, 1), Tmp1); AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
return Op.ResNo ? Tmp1 : Result; return Op.ResNo ? Tmp1 : Result;
} }
case ISD::FLT_ROUNDS: { case ISD::FLT_ROUNDS_: {
MVT::ValueType VT = Node->getValueType(0); MVT::ValueType VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) { switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action not supported for this op yet!"); default: assert(0 && "This action not supported for this op yet!");

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -3808,7 +3808,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
case ISD::TRUNCATE: return "truncate"; case ISD::TRUNCATE: return "truncate";
case ISD::FP_ROUND: return "fp_round"; case ISD::FP_ROUND: return "fp_round";
case ISD::FLT_ROUNDS: return "flt_rounds"; case ISD::FLT_ROUNDS_: return "flt_rounds";
case ISD::FP_ROUND_INREG: return "fp_round_inreg"; case ISD::FP_ROUND_INREG: return "fp_round_inreg";
case ISD::FP_EXTEND: return "fp_extend"; case ISD::FP_EXTEND: return "fp_extend";

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -2925,7 +2925,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0; return 0;
case Intrinsic::flt_rounds: { case Intrinsic::flt_rounds: {
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
return 0; return 0;
} }

6
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -111,7 +111,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand); setOperationAction(ISD::FPOW , MVT::f32, Expand);
setOperationAction(ISD::FLT_ROUNDS, MVT::i32, Custom); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
// If we're enabling GP optimizations, use hardware square root // If we're enabling GP optimizations, use hardware square root
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
@ -2215,7 +2215,7 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
return FP; return FP;
} }
static SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) { static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
/* /*
The rounding mode is in bits 30:31 of FPSR, and has the following The rounding mode is in bits 30:31 of FPSR, and has the following
settings: settings:
@ -3096,7 +3096,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
// Lower 64-bit shifts. // Lower 64-bit shifts.
case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);

6
lib/Target/X86/X86ISelLowering.cpp
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@ -216,7 +216,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand);
setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom); setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
setOperationAction(ISD::CTPOP , MVT::i8 , Expand); setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
setOperationAction(ISD::CTTZ , MVT::i8 , Custom); setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
@ -5048,7 +5048,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
} }
} }
SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) { SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
/* /*
The rounding mode is in bits 11:10 of FPSR, and has the following The rounding mode is in bits 11:10 of FPSR, and has the following
settings: settings:
@ -5209,7 +5209,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
case ISD::CTLZ: return LowerCTLZ(Op, DAG); case ISD::CTLZ: return LowerCTLZ(Op, DAG);
case ISD::CTTZ: return LowerCTTZ(Op, DAG); case ISD::CTTZ: return LowerCTTZ(Op, DAG);

2
lib/Target/X86/X86ISelLowering.h
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@ -525,7 +525,7 @@ namespace llvm {
SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG); SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG); SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG); SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG); SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);