mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
[AArch64] Match float round and convert to int instructions.
Summary: Add patterns for doing floating point round with various rounding modes followed by conversion to int as a single FCVT* instruction. Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D11424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243422 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Geoff Berry
parent
8d1cf2218d
commit
1a0868d554
@ -155,6 +155,7 @@ public:
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SDNode *SelectBitfieldInsertOp(SDNode *N);
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SDNode *SelectLIBM(SDNode *N);
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SDNode *SelectFPConvertWithRound(SDNode *N);
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SDNode *SelectReadRegister(SDNode *N);
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SDNode *SelectWriteRegister(SDNode *N);
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@ -185,6 +186,9 @@ private:
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}
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bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
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SDNode *GenerateInexactFlagIfNeeded(const SDValue &In, unsigned InTyVariant,
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SDLoc DL);
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};
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} // end anonymous namespace
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@ -2016,11 +2020,29 @@ SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
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return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
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}
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/// GenerateInexactFlagIfNeeded - Insert FRINTX instruction to generate inexact
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/// signal on round-to-integer operations if needed. C11 leaves it
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/// implementation-defined whether these operations trigger an inexact
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/// exception. IEEE says they don't. Unfortunately, Darwin decided they do so
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/// we sometimes have to insert a special instruction just to set the right bit
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/// in FPSR.
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SDNode *AArch64DAGToDAGISel::GenerateInexactFlagIfNeeded(const SDValue &In,
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unsigned InTyVariant,
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SDLoc DL) {
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if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
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// Pick the right FRINTX using InTyVariant needed to set the flags.
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// InTyVariant is 0 for 32-bit and 1 for 64-bit.
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unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
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return CurDAG->getMachineNode(FRINTXOpcs[InTyVariant], DL,
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In.getValueType(), MVT::Glue, In);
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}
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return nullptr;
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}
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SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
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EVT VT = N->getValueType(0);
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unsigned Variant;
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unsigned Opc;
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unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
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if (VT == MVT::f32) {
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Variant = 0;
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@ -2029,9 +2051,6 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
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} else
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return nullptr; // Unrecognized argument type. Fall back on default codegen.
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// Pick the FRINTX variant needed to set the flags.
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unsigned FRINTXOpc = FRINTXOpcs[Variant];
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switch (N->getOpcode()) {
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default:
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return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
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@ -2062,18 +2081,97 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
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SmallVector<SDValue, 2> Ops;
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Ops.push_back(In);
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// C11 leaves it implementation-defined whether these operations trigger an
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// inexact exception. IEEE says they don't. Unfortunately, Darwin decided
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// they do so we sometimes have to insert a special instruction just to set
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// the right bit in FPSR.
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if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
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SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
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Ops.push_back(SDValue(FRINTX, 1));
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}
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if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, Variant, dl))
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Ops.push_back(SDValue(FRINTXNode, 1));
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return CurDAG->getMachineNode(Opc, dl, VT, Ops);
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}
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/// SelectFPConvertWithRound - Try to combine FP rounding and
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/// FP-INT conversion.
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SDNode *AArch64DAGToDAGISel::SelectFPConvertWithRound(SDNode *N) {
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SDNode *Op0 = N->getOperand(0).getNode();
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// Return if the round op is used by other nodes, as this would result in two
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// FRINTX, one each for round and convert.
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if (!Op0->hasOneUse())
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return nullptr;
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unsigned InTyVariant;
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EVT InTy = Op0->getValueType(0);
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if (InTy == MVT::f32)
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InTyVariant = 0;
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else if (InTy == MVT::f64)
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InTyVariant = 1;
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else
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return nullptr;
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unsigned OutTyVariant;
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EVT OutTy = N->getValueType(0);
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if (OutTy == MVT::i32)
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OutTyVariant = 0;
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else if (OutTy == MVT::i64)
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OutTyVariant = 1;
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else
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return nullptr;
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assert((N->getOpcode() == ISD::FP_TO_SINT
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|| N->getOpcode() == ISD::FP_TO_UINT) && "Unexpected opcode!");
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unsigned FpConVariant = N->getOpcode() == ISD::FP_TO_SINT ? 0 : 1;
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unsigned Opc;
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switch (Op0->getOpcode()) {
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default:
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return nullptr;
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case ISD::FCEIL: {
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unsigned FCVTPOpcs[2][2][2] = {
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{ { AArch64::FCVTPSUWSr, AArch64::FCVTPSUXSr },
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{ AArch64::FCVTPSUWDr, AArch64::FCVTPSUXDr } },
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{ { AArch64::FCVTPUUWSr, AArch64::FCVTPUUXSr },
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{ AArch64::FCVTPUUWDr, AArch64::FCVTPUUXDr } } };
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Opc = FCVTPOpcs[FpConVariant][InTyVariant][OutTyVariant];
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break;
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}
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case ISD::FFLOOR: {
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unsigned FCVTMOpcs[2][2][2] = {
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{ { AArch64::FCVTMSUWSr, AArch64::FCVTMSUXSr },
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{ AArch64::FCVTMSUWDr, AArch64::FCVTMSUXDr } },
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{ { AArch64::FCVTMUUWSr, AArch64::FCVTMUUXSr },
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{ AArch64::FCVTMUUWDr, AArch64::FCVTMUUXDr } } };
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Opc = FCVTMOpcs[FpConVariant][InTyVariant][OutTyVariant];
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break;
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}
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case ISD::FTRUNC: {
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unsigned FCVTZOpcs[2][2][2] = {
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{ { AArch64::FCVTZSUWSr, AArch64::FCVTZSUXSr },
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{ AArch64::FCVTZSUWDr, AArch64::FCVTZSUXDr } },
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{ { AArch64::FCVTZUUWSr, AArch64::FCVTZUUXSr },
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{ AArch64::FCVTZUUWDr, AArch64::FCVTZUUXDr } } };
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Opc = FCVTZOpcs[FpConVariant][InTyVariant][OutTyVariant];
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break;
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}
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case ISD::FROUND: {
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unsigned FCVTAOpcs[2][2][2] = {
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{ { AArch64::FCVTASUWSr, AArch64::FCVTASUXSr },
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{ AArch64::FCVTASUWDr, AArch64::FCVTASUXDr } },
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{ { AArch64::FCVTAUUWSr, AArch64::FCVTAUUXSr },
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{ AArch64::FCVTAUUWDr, AArch64::FCVTAUUXDr } } };
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Opc = FCVTAOpcs[FpConVariant][InTyVariant][OutTyVariant];
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break;
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}
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}
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SDLoc DL(N);
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SDValue In = Op0->getOperand(0);
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SmallVector<SDValue, 2> Ops;
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Ops.push_back(In);
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if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, InTyVariant, DL))
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Ops.push_back(SDValue(FRINTXNode, 1));
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return CurDAG->getMachineNode(Opc, DL, OutTy, Ops);
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}
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bool
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AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
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unsigned RegWidth) {
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@ -3226,6 +3324,12 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
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if (SDNode *I = SelectLIBM(Node))
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return I;
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break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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if (SDNode *I = SelectFPConvertWithRound(Node))
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return I;
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break;
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}
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// Select the default instruction
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461
test/CodeGen/AArch64/round-conv.ll
Normal file
461
test/CodeGen/AArch64/round-conv.ll
Normal file
@ -0,0 +1,461 @@
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK-INEXACT
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECK-FAST
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; CHECK-INEXACT-LABEL: testmsws:
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; CHECK-INEXACT: fcvtms w0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testmsws:
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; CHECK-FAST: fcvtms w0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i32 @testmsws(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptosi float %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testmsxs:
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; CHECK-INEXACT: fcvtms x0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testmsxs:
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; CHECK-FAST: fcvtms x0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i64 @testmsxs(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptosi float %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testmswd:
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; CHECK-INEXACT: fcvtms w0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testmswd:
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; CHECK-FAST: fcvtms w0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i32 @testmswd(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptosi double %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testmsxd:
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; CHECK-INEXACT: fcvtms x0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testmsxd:
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; CHECK-FAST: fcvtms x0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i64 @testmsxd(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptosi double %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testmuws:
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; CHECK-INEXACT: fcvtmu w0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testmuws:
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; CHECK-FAST: fcvtmu w0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i32 @testmuws(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptoui float %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testmuxs:
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; CHECK-INEXACT: fcvtmu x0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testmuxs:
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; CHECK-FAST: fcvtmu x0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i64 @testmuxs(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptoui float %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testmuwd:
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; CHECK-INEXACT: fcvtmu w0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testmuwd:
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; CHECK-FAST: fcvtmu w0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i32 @testmuwd(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptoui double %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testmuxd:
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; CHECK-INEXACT: fcvtmu x0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testmuxd:
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; CHECK-FAST: fcvtmu x0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i64 @testmuxd(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptoui double %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testpsws:
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; CHECK-INEXACT: fcvtps w0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testpsws:
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; CHECK-FAST: fcvtps w0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i32 @testpsws(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptosi float %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testpsxs:
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; CHECK-INEXACT: fcvtps x0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testpsxs:
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; CHECK-FAST: fcvtps x0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i64 @testpsxs(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptosi float %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testpswd:
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; CHECK-INEXACT: fcvtps w0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testpswd:
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; CHECK-FAST: fcvtps w0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i32 @testpswd(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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%conv = fptosi double %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testpsxd:
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; CHECK-INEXACT: fcvtps x0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testpsxd:
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; CHECK-FAST: fcvtps x0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i64 @testpsxd(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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%conv = fptosi double %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testpuws:
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; CHECK-INEXACT: fcvtpu w0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testpuws:
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; CHECK-FAST: fcvtpu w0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i32 @testpuws(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptoui float %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testpuxs:
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; CHECK-INEXACT: fcvtpu x0, s0
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; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
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; CHECK-FAST-LABEL: testpuxs:
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; CHECK-FAST: fcvtpu x0, s0
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; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
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define i64 @testpuxs(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptoui float %call to i64
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ret i64 %conv
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}
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; CHECK-INEXACT-LABEL: testpuwd:
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; CHECK-INEXACT: fcvtpu w0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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; CHECK-FAST-LABEL: testpuwd:
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; CHECK-FAST: fcvtpu w0, d0
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; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
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define i32 @testpuwd(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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%conv = fptoui double %call to i32
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ret i32 %conv
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}
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; CHECK-INEXACT-LABEL: testpuxd:
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; CHECK-INEXACT: fcvtpu x0, d0
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; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
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||||
; CHECK-FAST-LABEL: testpuxd:
|
||||
; CHECK-FAST: fcvtpu x0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i64 @testpuxd(double %a) {
|
||||
entry:
|
||||
%call = call double @ceil(double %a) nounwind readnone
|
||||
%conv = fptoui double %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzsws:
|
||||
; CHECK-INEXACT: fcvtzs w0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testzsws:
|
||||
; CHECK-FAST: fcvtzs w0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i32 @testzsws(float %a) {
|
||||
entry:
|
||||
%call = call float @truncf(float %a) nounwind readnone
|
||||
%conv = fptosi float %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzsxs:
|
||||
; CHECK-INEXACT: fcvtzs x0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testzsxs:
|
||||
; CHECK-FAST: fcvtzs x0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i64 @testzsxs(float %a) {
|
||||
entry:
|
||||
%call = call float @truncf(float %a) nounwind readnone
|
||||
%conv = fptosi float %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzswd:
|
||||
; CHECK-INEXACT: fcvtzs w0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testzswd:
|
||||
; CHECK-FAST: fcvtzs w0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i32 @testzswd(double %a) {
|
||||
entry:
|
||||
%call = call double @trunc(double %a) nounwind readnone
|
||||
%conv = fptosi double %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzsxd:
|
||||
; CHECK-INEXACT: fcvtzs x0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testzsxd:
|
||||
; CHECK-FAST: fcvtzs x0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i64 @testzsxd(double %a) {
|
||||
entry:
|
||||
%call = call double @trunc(double %a) nounwind readnone
|
||||
%conv = fptosi double %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzuws:
|
||||
; CHECK-INEXACT: fcvtzu w0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testzuws:
|
||||
; CHECK-FAST: fcvtzu w0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i32 @testzuws(float %a) {
|
||||
entry:
|
||||
%call = call float @truncf(float %a) nounwind readnone
|
||||
%conv = fptoui float %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzuxs:
|
||||
; CHECK-INEXACT: fcvtzu x0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testzuxs:
|
||||
; CHECK-FAST: fcvtzu x0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i64 @testzuxs(float %a) {
|
||||
entry:
|
||||
%call = call float @truncf(float %a) nounwind readnone
|
||||
%conv = fptoui float %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzuwd:
|
||||
; CHECK-INEXACT: fcvtzu w0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testzuwd:
|
||||
; CHECK-FAST: fcvtzu w0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i32 @testzuwd(double %a) {
|
||||
entry:
|
||||
%call = call double @trunc(double %a) nounwind readnone
|
||||
%conv = fptoui double %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testzuxd:
|
||||
; CHECK-INEXACT: fcvtzu x0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testzuxd:
|
||||
; CHECK-FAST: fcvtzu x0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i64 @testzuxd(double %a) {
|
||||
entry:
|
||||
%call = call double @trunc(double %a) nounwind readnone
|
||||
%conv = fptoui double %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testasws:
|
||||
; CHECK-INEXACT: fcvtas w0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testasws:
|
||||
; CHECK-FAST: fcvtas w0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i32 @testasws(float %a) {
|
||||
entry:
|
||||
%call = call float @roundf(float %a) nounwind readnone
|
||||
%conv = fptosi float %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testasxs:
|
||||
; CHECK-INEXACT: fcvtas x0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testasxs:
|
||||
; CHECK-FAST: fcvtas x0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i64 @testasxs(float %a) {
|
||||
entry:
|
||||
%call = call float @roundf(float %a) nounwind readnone
|
||||
%conv = fptosi float %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testaswd:
|
||||
; CHECK-INEXACT: fcvtas w0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testaswd:
|
||||
; CHECK-FAST: fcvtas w0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i32 @testaswd(double %a) {
|
||||
entry:
|
||||
%call = call double @round(double %a) nounwind readnone
|
||||
%conv = fptosi double %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testasxd:
|
||||
; CHECK-INEXACT: fcvtas x0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testasxd:
|
||||
; CHECK-FAST: fcvtas x0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i64 @testasxd(double %a) {
|
||||
entry:
|
||||
%call = call double @round(double %a) nounwind readnone
|
||||
%conv = fptosi double %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testauws:
|
||||
; CHECK-INEXACT: fcvtau w0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testauws:
|
||||
; CHECK-FAST: fcvtau w0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i32 @testauws(float %a) {
|
||||
entry:
|
||||
%call = call float @roundf(float %a) nounwind readnone
|
||||
%conv = fptoui float %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testauxs:
|
||||
; CHECK-INEXACT: fcvtau x0, s0
|
||||
; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
|
||||
|
||||
; CHECK-FAST-LABEL: testauxs:
|
||||
; CHECK-FAST: fcvtau x0, s0
|
||||
; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
|
||||
define i64 @testauxs(float %a) {
|
||||
entry:
|
||||
%call = call float @roundf(float %a) nounwind readnone
|
||||
%conv = fptoui float %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testauwd:
|
||||
; CHECK-INEXACT: fcvtau w0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testauwd:
|
||||
; CHECK-FAST: fcvtau w0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i32 @testauwd(double %a) {
|
||||
entry:
|
||||
%call = call double @round(double %a) nounwind readnone
|
||||
%conv = fptoui double %call to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; CHECK-INEXACT-LABEL: testauxd:
|
||||
; CHECK-INEXACT: fcvtau x0, d0
|
||||
; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
|
||||
|
||||
; CHECK-FAST-LABEL: testauxd:
|
||||
; CHECK-FAST: fcvtau x0, d0
|
||||
; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
|
||||
define i64 @testauxd(double %a) {
|
||||
entry:
|
||||
%call = call double @round(double %a) nounwind readnone
|
||||
%conv = fptoui double %call to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
|
||||
declare float @floorf(float) nounwind readnone
|
||||
declare double @floor(double) nounwind readnone
|
||||
declare float @ceilf(float) nounwind readnone
|
||||
declare double @ceil(double) nounwind readnone
|
||||
declare float @truncf(float) nounwind readnone
|
||||
declare double @trunc(double) nounwind readnone
|
||||
declare float @roundf(float) nounwind readnone
|
||||
declare double @round(double) nounwind readnone
|
||||
Loading…
Reference in New Issue
Block a user