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Avoid scoping issues, fix buildbots

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103530 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-05-12 00:11:19 +00:00
parent a6cb641f48
commit 1a1ad578a3
1 changed files with 21 additions and 20 deletions
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41
lib/CodeGen/RegAllocFast.cpp
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@@ -182,9 +182,9 @@ void RAFast::killVirtReg(unsigned VirtReg) {
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"killVirtReg needs a virtual register"); "killVirtReg needs a virtual register");
DEBUG(dbgs() << " Killing %reg" << VirtReg << "\n"); DEBUG(dbgs() << " Killing %reg" << VirtReg << "\n");
LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg); LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
if (i != LiveVirtRegs.end()) if (lri != LiveVirtRegs.end())
killVirtReg(i); killVirtReg(lri);
} }
/// spillVirtReg - This method spills the value specified by VirtReg into the /// spillVirtReg - This method spills the value specified by VirtReg into the
@@ -195,9 +195,9 @@ void RAFast::spillVirtReg(MachineBasicBlock &MBB,
unsigned VirtReg, bool isKill) { unsigned VirtReg, bool isKill) {
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"Spilling a physical register is illegal!"); "Spilling a physical register is illegal!");
LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg); LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
assert(i != LiveVirtRegs.end() && "Spilling unmapped virtual register"); assert(lri != LiveVirtRegs.end() && "Spilling unmapped virtual register");
LiveReg &LR = i->second; LiveReg &LR = lri->second;
assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping"); assert(PhysRegState[LR.PhysReg] == VirtReg && "Broken RegState mapping");
// If this physreg is used by the instruction, we want to kill it on the // If this physreg is used by the instruction, we want to kill it on the
@@ -225,7 +225,7 @@ void RAFast::spillVirtReg(MachineBasicBlock &MBB,
} }
if (isKill) if (isKill)
killVirtReg(i); killVirtReg(lri);
} }
/// spillAll - Spill all dirty virtregs without killing them. /// spillAll - Spill all dirty virtregs without killing them.
@@ -442,10 +442,10 @@ unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum, unsigned VirtReg) { unsigned OpNum, unsigned VirtReg) {
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"Not a virtual register"); "Not a virtual register");
LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg); LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
if (i == LiveVirtRegs.end()) if (lri == LiveVirtRegs.end())
i = allocVirtReg(MBB, MI, VirtReg); lri = allocVirtReg(MBB, MI, VirtReg);
LiveReg &LR = i->second; LiveReg &LR = lri->second;
LR.LastUse = MI; LR.LastUse = MI;
LR.LastOpNum = OpNum; LR.LastOpNum = OpNum;
LR.Dirty = true; LR.Dirty = true;
@@ -458,17 +458,18 @@ unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum, unsigned VirtReg) { unsigned OpNum, unsigned VirtReg) {
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"Not a virtual register"); "Not a virtual register");
LiveRegMap::iterator i = LiveVirtRegs.find(VirtReg); LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
if (i == LiveVirtRegs.end()) { if (lri == LiveVirtRegs.end()) {
i = allocVirtReg(MBB, MI, VirtReg); lri = allocVirtReg(MBB, MI, VirtReg);
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC); int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into " DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
<< TRI->getName(i->second.PhysReg) << "\n"); << TRI->getName(lri->second.PhysReg) << "\n");
TII->loadRegFromStackSlot(MBB, MI, i->second.PhysReg, FrameIndex, RC, TRI); TII->loadRegFromStackSlot(MBB, MI, lri->second.PhysReg, FrameIndex, RC,
TRI);
++NumLoads; ++NumLoads;
} }
LiveReg &LR = i->second; LiveReg &LR = lri->second;
LR.LastUse = MI; LR.LastUse = MI;
LR.LastOpNum = OpNum; LR.LastOpNum = OpNum;
UsedInInstr.set(LR.PhysReg); UsedInInstr.set(LR.PhysReg);
@@ -584,9 +585,9 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (!MO.isReg()) continue; if (!MO.isReg()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
LiveRegMap::iterator it = LiveVirtRegs.find(Reg); LiveRegMap::iterator lri = LiveVirtRegs.find(Reg);
if (it != LiveVirtRegs.end()) if (lri != LiveVirtRegs.end())
setPhysReg(MO, it->second.PhysReg); setPhysReg(MO, lri->second.PhysReg);
else else
MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry! MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
} }