mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
CellSPU:
- Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel
parent
de5debfb58
commit
1a6cdb6b50
@ -593,8 +593,8 @@ SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
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&& !SelectDFormAddr(Op, N, Base, Index)) {
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// If the address is neither A-form or D-form, punt and use an X-form
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// address:
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Base = N.getOperand(0);
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Index = N.getOperand(1);
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Base = N.getOperand(1);
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Index = N.getOperand(0);
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return true;
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}
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@ -759,12 +759,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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}
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SDValue insertEltOp =
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DAG.getNode(SPUISD::SHUFFLE_MASK, stVecVT, insertEltPtr);
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DAG.getNode(SPUISD::SHUFFLE_MASK, vecVT, insertEltPtr);
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SDValue vectorizeOp =
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DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue);
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result = DAG.getNode(SPUISD::SHUFB, vecVT, vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, vecVT, insertEltOp));
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result = DAG.getNode(SPUISD::SHUFB, vecVT,
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vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
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result = DAG.getStore(the_chain, result, basePtr,
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LN->getSrcValue(), LN->getSrcValueOffset(),
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@ -885,10 +886,10 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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static SDValue
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LowerConstant(SDValue Op, SelectionDAG &DAG) {
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MVT VT = Op.getValueType();
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ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
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if (VT == MVT::i64) {
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SDValue T = DAG.getConstant(CN->getZExtValue(), MVT::i64);
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ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
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SDValue T = DAG.getConstant(CN->getZExtValue(), VT);
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return DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
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} else {
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@ -906,15 +907,18 @@ LowerConstant(SDValue Op, SelectionDAG &DAG) {
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static SDValue
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LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
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MVT VT = Op.getValueType();
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ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
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assert((FP != 0) &&
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"LowerConstantFP: Node is not ConstantFPSDNode");
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if (VT == MVT::f64) {
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ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
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assert((FP != 0) &&
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"LowerConstantFP: Node is not ConstantFPSDNode");
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uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
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return DAG.getNode(ISD::BIT_CONVERT, VT,
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LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
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SDValue T = DAG.getConstant(dbits, MVT::i64);
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SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T);
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return DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Tvec));
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}
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return SDValue();
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@ -1793,7 +1797,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT));
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// Copy register's contents as index in SHUFFLE_MASK:
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SDValue ShufMaskOp =
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DAG.getNode(SPUISD::SHUFFLE_MASK, V1.getValueType(),
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DAG.getNode(SPUISD::SHUFFLE_MASK, MVT::v4i32,
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DAG.getTargetConstant(V2Elt, MVT::i32),
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DAG.getCopyFromReg(InitTempReg, VReg, PtrVT));
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// Use shuffle mask in SHUFB synthetic instruction:
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@ -1818,7 +1822,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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}
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SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
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&ResultMask[0], ResultMask.size());
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&ResultMask[0], ResultMask.size());
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return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask);
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}
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}
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@ -2165,7 +2169,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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if (scaleShift > 0) {
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// Scale the shift factor:
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Elt = DAG.getNode(ISD::SHL, MVT::i32, Elt,
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DAG.getConstant(scaleShift, MVT::i32));
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DAG.getConstant(scaleShift, MVT::i32));
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}
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vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, VecVT, N, Elt);
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@ -2209,7 +2213,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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}
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retval = DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
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DAG.getNode(SPUISD::SHUFB, VecVT, vecShift, vecShift, replicate));
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DAG.getNode(SPUISD::SHUFB, VecVT,
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vecShift, vecShift, replicate));
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}
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return retval;
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@ -2225,18 +2230,17 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
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MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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// Use $2 because it's always 16-byte aligned and it's available:
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SDValue PtrBase = DAG.getRegister(SPU::R2, PtrVT);
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// Use $sp ($1) because it's always 16-byte aligned and it's available:
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SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
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DAG.getRegister(SPU::R1, PtrVT),
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DAG.getConstant(CN->getSExtValue(), PtrVT));
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SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, VT, Pointer);
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SDValue result =
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DAG.getNode(SPUISD::SHUFB, VT,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
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VecOp,
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DAG.getNode(SPUISD::SHUFFLE_MASK, VT,
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DAG.getNode(ISD::ADD, PtrVT,
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PtrBase,
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DAG.getConstant(CN->getZExtValue(),
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PtrVT))));
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VecOp,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
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return result;
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}
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@ -2901,8 +2905,10 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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#endif
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const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
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SelectionDAG &DAG = DCI.DAG;
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SDValue Op0 = N->getOperand(0); // everything has at least one operand
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SDValue Result; // Initially, NULL result
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SDValue Op0 = N->getOperand(0); // everything has at least one operand
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MVT NodeVT = N->getValueType(0); // The node's value type
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MVT Op0VT = Op0.getValueType(); // The first operand's result
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SDValue Result; // Initially, empty result
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switch (N->getOpcode()) {
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default: break;
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@ -2918,14 +2924,13 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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ConstantSDNode *CN0 = cast<ConstantSDNode>(Op1);
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ConstantSDNode *CN1 = cast<ConstantSDNode>(Op01);
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SDValue combinedConst =
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DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(),
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Op0.getValueType());
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DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(), Op0VT);
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DEBUG(cerr << "Replace: (add " << CN0->getZExtValue() << ", "
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<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n");
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DEBUG(cerr << "With: (SPUindirect <arg>, "
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<< CN0->getZExtValue() + CN1->getZExtValue() << ")\n");
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return DAG.getNode(SPUISD::IndirectAddr, Op0.getValueType(),
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return DAG.getNode(SPUISD::IndirectAddr, Op0VT,
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Op0.getOperand(0), combinedConst);
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}
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} else if (isa<ConstantSDNode>(Op0)
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@ -2938,8 +2943,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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ConstantSDNode *CN0 = cast<ConstantSDNode>(Op0);
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ConstantSDNode *CN1 = cast<ConstantSDNode>(Op11);
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SDValue combinedConst =
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DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(),
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Op0.getValueType());
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DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(), Op0VT);
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DEBUG(cerr << "Replace: (add " << CN0->getZExtValue() << ", "
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<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n");
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@ -2955,8 +2959,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND: {
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if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT &&
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N->getValueType(0) == Op0.getValueType()) {
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if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) {
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// (any_extend (SPUextract_elt0 <arg>)) ->
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// (SPUextract_elt0 <arg>)
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// Types must match, however...
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@ -3000,7 +3003,6 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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if (isa<ConstantSDNode>(Op1)) {
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// Kill degenerate vector shifts:
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ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
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if (CN->getZExtValue() == 0) {
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Result = Op0;
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}
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@ -3014,20 +3016,20 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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case ISD::ANY_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::SIGN_EXTEND: {
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// (SPUpromote_scalar (any|sign|zero_extend (SPUextract_elt0 <arg>))) ->
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// (SPUpromote_scalar (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
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// <arg>
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// but only if the SPUpromote_scalar and <arg> types match.
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SDValue Op00 = Op0.getOperand(0);
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if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
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SDValue Op000 = Op00.getOperand(0);
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if (Op000.getValueType() == N->getValueType(0)) {
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if (Op000.getValueType() == NodeVT) {
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Result = Op000;
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}
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}
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break;
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}
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case SPUISD::VEC2PREFSLOT: {
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// (SPUpromote_scalar (SPUextract_elt0 <arg>)) ->
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// (SPUpromote_scalar (SPUvec2prefslot <arg>)) ->
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// <arg>
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Result = Op0.getOperand(0);
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break;
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@ -3037,7 +3039,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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}
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}
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// Otherwise, return unchanged.
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#ifdef NDEBUG
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#ifndef NDEBUG
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if (Result.getNode()) {
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DEBUG(cerr << "\nReplace.SPU: ");
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DEBUG(N->dump(&DAG));
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@ -269,52 +269,51 @@ def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
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// Generate Controls for Insertion:
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//===----------------------------------------------------------------------===//
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def CBD :
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RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cbd\t$rT, $src", ShuffleOp,
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[(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CBD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cbd\t$rT, $src", ShuffleOp,
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[(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CBX: RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
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"cbx\t$rT, $src", ShuffleOp,
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[(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
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def CHD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
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"chd\t$rT, $src", ShuffleOp,
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[(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CHX: RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
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"chx\t$rT, $src", ShuffleOp,
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[(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
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def CWD: RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cwd\t$rT, $src", ShuffleOp,
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[(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CWDf32 : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cwd\t$rT, $src", ShuffleOp,
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[(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CWX: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
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"cwx\t$rT, $src", ShuffleOp,
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[(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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def CWXf32 : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CWDf32: RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cwd\t$rT, $src", ShuffleOp,
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[(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CWXf32: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
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"cwx\t$rT, $src", ShuffleOp,
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[(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
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def CDD: RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cdd\t$rT, $src", ShuffleOp,
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[(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CDDf64 : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cdd\t$rT, $src", ShuffleOp,
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[(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CDX: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
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"cdx\t$rT, $src", ShuffleOp,
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[(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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def CDXf64 : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
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def CDDf64: RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
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"cdd\t$rT, $src", ShuffleOp,
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[(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
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def CDXf64: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
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"cdx\t$rT, $src", ShuffleOp,
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[(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
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@ -1786,46 +1785,33 @@ class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
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RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
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IntegerOp, pattern>;
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class SHUFBVecInst<ValueType vectype>:
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class SHUFBVecInst<ValueType resultvec, ValueType maskvec>:
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SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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[(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
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(vectype VECREG:$rB),
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(vectype VECREG:$rC)))]>;
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// It's this pattern that's probably the most useful, since SPUISelLowering
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// methods create a v16i8 vector for $rC:
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class SHUFBVecPat1<ValueType vectype, ValueType masktype, SPUInstr inst>:
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Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
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(masktype VECREG:$rC)),
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(inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
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[(set (resultvec VECREG:$rT),
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(SPUshuffle (resultvec VECREG:$rA),
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(resultvec VECREG:$rB),
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(maskvec VECREG:$rC)))]>;
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multiclass ShuffleBytes
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{
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def v16i8 : SHUFBVecInst<v16i8>;
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def v8i16 : SHUFBVecInst<v8i16>;
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def v4i32 : SHUFBVecInst<v4i32>;
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def v2i64 : SHUFBVecInst<v2i64>;
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def v16i8 : SHUFBVecInst<v16i8, v16i8>;
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def v16i8_m32 : SHUFBVecInst<v16i8, v4i32>;
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def v8i16 : SHUFBVecInst<v8i16, v16i8>;
|
||||
def v8i16_m32 : SHUFBVecInst<v8i16, v4i32>;
|
||||
def v4i32 : SHUFBVecInst<v4i32, v16i8>;
|
||||
def v4i32_m32 : SHUFBVecInst<v4i32, v4i32>;
|
||||
def v2i64 : SHUFBVecInst<v2i64, v16i8>;
|
||||
def v2i64_m32 : SHUFBVecInst<v2i64, v4i32>;
|
||||
|
||||
def v4f32 : SHUFBVecInst<v4f32>;
|
||||
def v2f64 : SHUFBVecInst<v2f64>;
|
||||
def v4f32 : SHUFBVecInst<v4f32, v16i8>;
|
||||
def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>;
|
||||
|
||||
def v2f64 : SHUFBVecInst<v2f64, v16i8>;
|
||||
def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>;
|
||||
}
|
||||
|
||||
defm SHUFB : ShuffleBytes;
|
||||
|
||||
// Shuffle mask is a v16i8 vector
|
||||
def : SHUFBVecPat1<v8i16, v16i8, SHUFBv16i8>;
|
||||
def : SHUFBVecPat1<v4i32, v16i8, SHUFBv16i8>;
|
||||
def : SHUFBVecPat1<v2i64, v16i8, SHUFBv16i8>;
|
||||
def : SHUFBVecPat1<v4f32, v16i8, SHUFBv16i8>;
|
||||
def : SHUFBVecPat1<v2f64, v16i8, SHUFBv16i8>;
|
||||
|
||||
// Shuffle mask is a v4i32 vector:
|
||||
def : SHUFBVecPat1<v16i8, v4i32, SHUFBv4i32>;
|
||||
def : SHUFBVecPat1<v8i16, v4i32, SHUFBv4i32>;
|
||||
def : SHUFBVecPat1<v2i64, v4i32, SHUFBv4i32>;
|
||||
def : SHUFBVecPat1<v4f32, v4i32, SHUFBv4i32>;
|
||||
def : SHUFBVecPat1<v2f64, v4i32, SHUFBv4i32>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Shift and rotate group:
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
||||
; RUN: grep cbd %t1.s | count 3
|
||||
; RUN: grep chd %t1.s | count 3
|
||||
; RUN: grep cwd %t1.s | count 6
|
||||
; RUN: grep il %t1.s | count 4
|
||||
; RUN: grep ilh %t1.s | count 3
|
||||
; RUN: grep cbd %t1.s | count 5
|
||||
; RUN: grep chd %t1.s | count 5
|
||||
; RUN: grep cwd %t1.s | count 10
|
||||
; RUN: grep il %t1.s | count 15
|
||||
; RUN: grep ilh %t1.s | count 10
|
||||
; RUN: grep iohl %t1.s | count 1
|
||||
; RUN: grep ilhu %t1.s | count 1
|
||||
; RUN: grep shufb %t1.s | count 12
|
||||
; RUN: grep ilhu %t1.s | count 4
|
||||
; RUN: grep shufb %t1.s | count 26
|
||||
; RUN: grep 17219 %t1.s | count 1
|
||||
; RUN: grep 22598 %t1.s | count 1
|
||||
; RUN: grep -- -39 %t1.s | count 1
|
||||
@ -51,3 +51,70 @@ entry:
|
||||
%tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
|
||||
ret <4 x i32> %tmp1.2
|
||||
}
|
||||
|
||||
define void @variable_v16i8_1(<16 x i8>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <16 x i8>* %a, i32 %i
|
||||
%tmp2 = load <16 x i8>* %arrayidx
|
||||
%tmp3 = insertelement <16 x i8> %tmp2, i8 1, i32 1
|
||||
%tmp8 = insertelement <16 x i8> %tmp3, i8 2, i32 11
|
||||
store <16 x i8> %tmp8, <16 x i8>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v8i16_1(<8 x i16>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <8 x i16>* %a, i32 %i
|
||||
%tmp2 = load <8 x i16>* %arrayidx
|
||||
%tmp3 = insertelement <8 x i16> %tmp2, i16 1, i32 1
|
||||
%tmp8 = insertelement <8 x i16> %tmp3, i16 2, i32 6
|
||||
store <8 x i16> %tmp8, <8 x i16>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v4i32_1(<4 x i32>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <4 x i32>* %a, i32 %i
|
||||
%tmp2 = load <4 x i32>* %arrayidx
|
||||
%tmp3 = insertelement <4 x i32> %tmp2, i32 1, i32 1
|
||||
%tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
|
||||
store <4 x i32> %tmp8, <4 x i32>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v4f32_1(<4 x float>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <4 x float>* %a, i32 %i
|
||||
%tmp2 = load <4 x float>* %arrayidx
|
||||
%tmp3 = insertelement <4 x float> %tmp2, float 1.000000e+00, i32 1
|
||||
%tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
|
||||
store <4 x float> %tmp8, <4 x float>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v2i64_1(<2 x i64>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <2 x i64>* %a, i32 %i
|
||||
%tmp2 = load <2 x i64>* %arrayidx
|
||||
%tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 0
|
||||
store <2 x i64> %tmp3, <2 x i64>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v2i64_2(<2 x i64>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <2 x i64>* %a, i32 %i
|
||||
%tmp2 = load <2 x i64>* %arrayidx
|
||||
%tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 1
|
||||
store <2 x i64> %tmp3, <2 x i64>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @variable_v2f64_1(<2 x double>* %a, i32 %i) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <2 x double>* %a, i32 %i
|
||||
%tmp2 = load <2 x double>* %arrayidx
|
||||
%tmp3 = insertelement <2 x double> %tmp2, double 1.000000e+00, i32 1
|
||||
store <2 x double> %tmp3, <2 x double>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user