mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
0aa2b8800c
commit
1a7eab3878
@ -83,6 +83,30 @@ def getPredOpcode : InstrMapping {
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let ValueCols = [["true"], ["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-true instructions with their
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// predicate-false forms
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//
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def getFalsePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
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let ColFields = ["PredSense"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-false instructions with their
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// predicate-true forms
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//
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def getTruePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
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let ColFields = ["PredSense"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicated instructions with their .new
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// format.
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@ -626,110 +626,8 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
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return false;
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}
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bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default: return false;
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// JMP_EQri
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case Hexagon::JMP_EQriPt_nv_V4:
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case Hexagon::JMP_EQriPnt_nv_V4:
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case Hexagon::JMP_EQriNotPt_nv_V4:
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case Hexagon::JMP_EQriNotPnt_nv_V4:
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case Hexagon::JMP_EQriPt_ie_nv_V4:
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case Hexagon::JMP_EQriPnt_ie_nv_V4:
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case Hexagon::JMP_EQriNotPt_ie_nv_V4:
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case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
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// JMP_EQri - with -1
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case Hexagon::JMP_EQriPtneg_nv_V4:
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case Hexagon::JMP_EQriPntneg_nv_V4:
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case Hexagon::JMP_EQriNotPtneg_nv_V4:
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case Hexagon::JMP_EQriNotPntneg_nv_V4:
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case Hexagon::JMP_EQriPtneg_ie_nv_V4:
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case Hexagon::JMP_EQriPntneg_ie_nv_V4:
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case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
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case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
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// JMP_EQrr
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case Hexagon::JMP_EQrrPt_nv_V4:
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case Hexagon::JMP_EQrrPnt_nv_V4:
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case Hexagon::JMP_EQrrNotPt_nv_V4:
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case Hexagon::JMP_EQrrNotPnt_nv_V4:
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case Hexagon::JMP_EQrrPt_ie_nv_V4:
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case Hexagon::JMP_EQrrPnt_ie_nv_V4:
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case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
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case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
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// JMP_GTri
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case Hexagon::JMP_GTriPt_nv_V4:
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case Hexagon::JMP_GTriPnt_nv_V4:
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case Hexagon::JMP_GTriNotPt_nv_V4:
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case Hexagon::JMP_GTriNotPnt_nv_V4:
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case Hexagon::JMP_GTriPt_ie_nv_V4:
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case Hexagon::JMP_GTriPnt_ie_nv_V4:
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case Hexagon::JMP_GTriNotPt_ie_nv_V4:
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case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
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// JMP_GTri - with -1
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case Hexagon::JMP_GTriPtneg_nv_V4:
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case Hexagon::JMP_GTriPntneg_nv_V4:
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case Hexagon::JMP_GTriNotPtneg_nv_V4:
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case Hexagon::JMP_GTriNotPntneg_nv_V4:
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case Hexagon::JMP_GTriPtneg_ie_nv_V4:
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case Hexagon::JMP_GTriPntneg_ie_nv_V4:
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case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
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case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
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// JMP_GTrr
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case Hexagon::JMP_GTrrPt_nv_V4:
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case Hexagon::JMP_GTrrPnt_nv_V4:
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case Hexagon::JMP_GTrrNotPt_nv_V4:
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case Hexagon::JMP_GTrrNotPnt_nv_V4:
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case Hexagon::JMP_GTrrPt_ie_nv_V4:
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case Hexagon::JMP_GTrrPnt_ie_nv_V4:
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case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
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case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
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// JMP_GTrrdn
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case Hexagon::JMP_GTrrdnPt_nv_V4:
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case Hexagon::JMP_GTrrdnPnt_nv_V4:
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case Hexagon::JMP_GTrrdnNotPt_nv_V4:
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case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
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case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
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case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
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case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
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case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
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// JMP_GTUri
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case Hexagon::JMP_GTUriPt_nv_V4:
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case Hexagon::JMP_GTUriPnt_nv_V4:
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case Hexagon::JMP_GTUriNotPt_nv_V4:
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case Hexagon::JMP_GTUriNotPnt_nv_V4:
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case Hexagon::JMP_GTUriPt_ie_nv_V4:
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case Hexagon::JMP_GTUriPnt_ie_nv_V4:
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case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
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case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
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// JMP_GTUrr
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case Hexagon::JMP_GTUrrPt_nv_V4:
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case Hexagon::JMP_GTUrrPnt_nv_V4:
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case Hexagon::JMP_GTUrrNotPt_nv_V4:
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case Hexagon::JMP_GTUrrNotPnt_nv_V4:
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case Hexagon::JMP_GTUrrPt_ie_nv_V4:
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case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
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case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
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case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
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// JMP_GTUrrdn
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case Hexagon::JMP_GTUrrdnPt_nv_V4:
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case Hexagon::JMP_GTUrrdnPnt_nv_V4:
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case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
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case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
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case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
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case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
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case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
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case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
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return true;
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}
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bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
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return MI->getDesc().isBranch();
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}
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bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
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@ -1033,6 +931,12 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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// cNotPt ---> cNotPt_nv
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// cPt ---> cPt_nv
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unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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int InvPredOpcode;
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InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
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: Hexagon::getTruePredOpcode(Opc);
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if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
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return InvPredOpcode;
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switch(Opc) {
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default: llvm_unreachable("Unexpected predicated instruction");
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case Hexagon::TFR_cPt:
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@ -1365,117 +1269,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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return Hexagon::DEALLOC_RET_cNotPt_V4;
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case Hexagon::DEALLOC_RET_cNotPt_V4:
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return Hexagon::DEALLOC_RET_cPt_V4;
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// New Value Jump.
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// JMPEQ_ri - with -1.
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case Hexagon::JMP_EQriPtneg_nv_V4:
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return Hexagon::JMP_EQriNotPtneg_nv_V4;
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case Hexagon::JMP_EQriNotPtneg_nv_V4:
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return Hexagon::JMP_EQriPtneg_nv_V4;
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case Hexagon::JMP_EQriPntneg_nv_V4:
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return Hexagon::JMP_EQriNotPntneg_nv_V4;
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case Hexagon::JMP_EQriNotPntneg_nv_V4:
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return Hexagon::JMP_EQriPntneg_nv_V4;
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// JMPEQ_ri.
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case Hexagon::JMP_EQriPt_nv_V4:
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return Hexagon::JMP_EQriNotPt_nv_V4;
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case Hexagon::JMP_EQriNotPt_nv_V4:
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return Hexagon::JMP_EQriPt_nv_V4;
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case Hexagon::JMP_EQriPnt_nv_V4:
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return Hexagon::JMP_EQriNotPnt_nv_V4;
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case Hexagon::JMP_EQriNotPnt_nv_V4:
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return Hexagon::JMP_EQriPnt_nv_V4;
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// JMPEQ_rr.
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case Hexagon::JMP_EQrrPt_nv_V4:
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return Hexagon::JMP_EQrrNotPt_nv_V4;
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case Hexagon::JMP_EQrrNotPt_nv_V4:
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return Hexagon::JMP_EQrrPt_nv_V4;
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case Hexagon::JMP_EQrrPnt_nv_V4:
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return Hexagon::JMP_EQrrNotPnt_nv_V4;
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case Hexagon::JMP_EQrrNotPnt_nv_V4:
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return Hexagon::JMP_EQrrPnt_nv_V4;
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// JMPGT_ri - with -1.
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case Hexagon::JMP_GTriPtneg_nv_V4:
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return Hexagon::JMP_GTriNotPtneg_nv_V4;
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case Hexagon::JMP_GTriNotPtneg_nv_V4:
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return Hexagon::JMP_GTriPtneg_nv_V4;
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case Hexagon::JMP_GTriPntneg_nv_V4:
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return Hexagon::JMP_GTriNotPntneg_nv_V4;
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case Hexagon::JMP_GTriNotPntneg_nv_V4:
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return Hexagon::JMP_GTriPntneg_nv_V4;
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// JMPGT_ri.
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case Hexagon::JMP_GTriPt_nv_V4:
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return Hexagon::JMP_GTriNotPt_nv_V4;
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case Hexagon::JMP_GTriNotPt_nv_V4:
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return Hexagon::JMP_GTriPt_nv_V4;
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case Hexagon::JMP_GTriPnt_nv_V4:
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return Hexagon::JMP_GTriNotPnt_nv_V4;
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case Hexagon::JMP_GTriNotPnt_nv_V4:
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return Hexagon::JMP_GTriPnt_nv_V4;
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// JMPGT_rr.
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case Hexagon::JMP_GTrrPt_nv_V4:
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return Hexagon::JMP_GTrrNotPt_nv_V4;
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case Hexagon::JMP_GTrrNotPt_nv_V4:
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return Hexagon::JMP_GTrrPt_nv_V4;
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case Hexagon::JMP_GTrrPnt_nv_V4:
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return Hexagon::JMP_GTrrNotPnt_nv_V4;
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case Hexagon::JMP_GTrrNotPnt_nv_V4:
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return Hexagon::JMP_GTrrPnt_nv_V4;
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// JMPGT_rrdn.
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case Hexagon::JMP_GTrrdnPt_nv_V4:
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return Hexagon::JMP_GTrrdnNotPt_nv_V4;
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case Hexagon::JMP_GTrrdnNotPt_nv_V4:
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return Hexagon::JMP_GTrrdnPt_nv_V4;
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case Hexagon::JMP_GTrrdnPnt_nv_V4:
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return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
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case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
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return Hexagon::JMP_GTrrdnPnt_nv_V4;
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// JMPGTU_ri.
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case Hexagon::JMP_GTUriPt_nv_V4:
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return Hexagon::JMP_GTUriNotPt_nv_V4;
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case Hexagon::JMP_GTUriNotPt_nv_V4:
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return Hexagon::JMP_GTUriPt_nv_V4;
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case Hexagon::JMP_GTUriPnt_nv_V4:
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return Hexagon::JMP_GTUriNotPnt_nv_V4;
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case Hexagon::JMP_GTUriNotPnt_nv_V4:
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return Hexagon::JMP_GTUriPnt_nv_V4;
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// JMPGTU_rr.
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case Hexagon::JMP_GTUrrPt_nv_V4:
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return Hexagon::JMP_GTUrrNotPt_nv_V4;
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case Hexagon::JMP_GTUrrNotPt_nv_V4:
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return Hexagon::JMP_GTUrrPt_nv_V4;
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case Hexagon::JMP_GTUrrPnt_nv_V4:
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return Hexagon::JMP_GTUrrNotPnt_nv_V4;
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case Hexagon::JMP_GTUrrNotPnt_nv_V4:
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return Hexagon::JMP_GTUrrPnt_nv_V4;
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// JMPGTU_rrdn.
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case Hexagon::JMP_GTUrrdnPt_nv_V4:
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return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
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case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
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return Hexagon::JMP_GTUrrdnPt_nv_V4;
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case Hexagon::JMP_GTUrrdnPnt_nv_V4:
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return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
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case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
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return Hexagon::JMP_GTUrrdnPnt_nv_V4;
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}
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}
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@ -1504,12 +1297,7 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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case Hexagon::JMP:
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return !invertPredicate ? Hexagon::JMP_t :
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Hexagon::JMP_f;
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case Hexagon::JMP_EQrrPt_nv_V4:
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return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
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Hexagon::JMP_EQrrNotPt_nv_V4;
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case Hexagon::JMP_EQriPt_nv_V4:
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return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
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Hexagon::JMP_EQriNotPt_nv_V4;
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case Hexagon::COMBINE_rr:
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return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
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Hexagon::COMBINE_rr_cNotPt;
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@ -1890,13 +1678,41 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
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return true;
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}
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// Returns true if an instruction is predicated irrespective of the predicate
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// sense. For example, all of the following will return true.
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// if (p0) R1 = add(R2, R3)
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// if (!p0) R1 = add(R2, R3)
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// if (p0.new) R1 = add(R2, R3)
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// if (!p0.new) R1 = add(R2, R3)
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bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
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}
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bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
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const uint64_t F = get(Opcode).TSFlags;
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return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
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}
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bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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assert(isPredicated(MI));
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return (!((F >> HexagonII::PredicatedFalsePos) &
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HexagonII::PredicatedFalseMask));
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}
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bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
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const uint64_t F = get(Opcode).TSFlags;
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// Make sure that the instruction is predicated.
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assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
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return (!((F >> HexagonII::PredicatedFalsePos) &
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HexagonII::PredicatedFalseMask));
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}
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bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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@ -1904,6 +1720,13 @@ bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
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return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
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}
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bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
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const uint64_t F = get(Opcode).TSFlags;
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assert(isPredicated(Opcode));
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return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
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}
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bool
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HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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@ -2372,6 +2195,18 @@ isConditionalStore (const MachineInstr* MI) const {
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}
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}
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bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
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if (isNewValue(MI) && isBranch(MI))
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return true;
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return false;
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}
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bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
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}
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// Returns true, if any one of the operands is a dot new
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// insn, whether it is predicated dot new or register dot new.
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bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
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@ -113,6 +113,7 @@ public:
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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virtual bool isBranch(const MachineInstr *MI) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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virtual bool
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PredicateInstruction(MachineInstr *MI,
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@ -129,7 +130,11 @@ public:
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const BranchProbability &Probability) const;
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|
||||
virtual bool isPredicated(const MachineInstr *MI) const;
|
||||
virtual bool isPredicated(unsigned Opcode) const;
|
||||
virtual bool isPredicatedTrue(const MachineInstr *MI) const;
|
||||
virtual bool isPredicatedTrue(unsigned Opcode) const;
|
||||
virtual bool isPredicatedNew(const MachineInstr *MI) const;
|
||||
virtual bool isPredicatedNew(unsigned Opcode) const;
|
||||
virtual bool DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const;
|
||||
virtual bool
|
||||
@ -178,6 +183,7 @@ public:
|
||||
bool isConditionalLoad (const MachineInstr* MI) const;
|
||||
bool isConditionalStore(const MachineInstr* MI) const;
|
||||
bool isNewValueInst(const MachineInstr* MI) const;
|
||||
bool isNewValue(const MachineInstr* MI) const;
|
||||
bool isDotNewInst(const MachineInstr* MI) const;
|
||||
bool isDeallocRet(const MachineInstr *MI) const;
|
||||
unsigned getInvertedPredicatedOpcode(const int Opc) const;
|
||||
|
||||
@ -967,180 +967,194 @@ defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
|
||||
// NV/J +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
|
||||
def _ie_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, $src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// multiclass/template class for the new-value compare jumps with the register
|
||||
// operands.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def _nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, $src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
|
||||
class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
|
||||
bit isNegCond, bit isTaken>
|
||||
: NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
||||
"if ("#!if(isNegCond, "!","")#mnemonic#
|
||||
"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
|
||||
"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
|
||||
#!if(isTaken, "t","nt")#" $offset",
|
||||
[]>, Requires<[HasV4T]> {
|
||||
|
||||
bits<5> src1;
|
||||
bits<5> src2;
|
||||
bits<3> Ns; // New-Value Operand
|
||||
bits<5> RegOp; // Non New-Value Operand
|
||||
bits<11> offset;
|
||||
|
||||
let isBrTaken = !if(isTaken, "true", "false");
|
||||
let isPredicatedFalse = isNegCond;
|
||||
|
||||
let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
|
||||
let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
|
||||
|
||||
let IClass = 0b0010;
|
||||
let Inst{26} = 0b0;
|
||||
let Inst{25-23} = majOp;
|
||||
let Inst{22} = isNegCond;
|
||||
let Inst{18-16} = Ns;
|
||||
let Inst{13} = isTaken;
|
||||
let Inst{12-8} = RegOp;
|
||||
let Inst{21-20} = offset{10-9};
|
||||
let Inst{7-1} = offset{8-2};
|
||||
}
|
||||
|
||||
multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
|
||||
string TakenStr> {
|
||||
def _ie_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1, $src2.new)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1, $src2.new)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
|
||||
bit isNegCond> {
|
||||
// Branch not taken:
|
||||
def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
|
||||
// Branch taken:
|
||||
def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
|
||||
}
|
||||
|
||||
multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
|
||||
def _ie_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
// NvOpNum = 0 -> First Operand is a new-value Register
|
||||
// NvOpNum = 1 -> Second Operand is a new-value Register
|
||||
|
||||
def _nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
|
||||
bit NvOpNum> {
|
||||
let BaseOpcode = BaseOp#_NVJ in {
|
||||
defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
|
||||
defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
|
||||
}
|
||||
}
|
||||
|
||||
multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
|
||||
def _ie_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
|
||||
|
||||
def _nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
|
||||
string TakenStr> {
|
||||
def _ie_nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _nv_V4 : NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
|
||||
!strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
|
||||
!strconcat("($src1.new, #$src2)) jump:",
|
||||
!strconcat(TakenStr, " $offset"))))),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
// Multiclass for regular dot new of Ist operand register.
|
||||
multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
|
||||
defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
|
||||
defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
|
||||
}
|
||||
|
||||
// Multiclass for dot new of 2nd operand register.
|
||||
multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
|
||||
defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
|
||||
defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
|
||||
}
|
||||
|
||||
// Multiclass for 2nd operand immediate, including -1.
|
||||
multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
|
||||
defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
|
||||
defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
|
||||
defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
|
||||
defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
|
||||
}
|
||||
|
||||
// Multiclass for 2nd operand immediate, excluding -1.
|
||||
multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
|
||||
defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
|
||||
defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
|
||||
}
|
||||
|
||||
// Multiclass for tstbit, where 2nd operand is always #0.
|
||||
multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
|
||||
defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
|
||||
defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
|
||||
}
|
||||
|
||||
// Multiclass for GT.
|
||||
multiclass NVJ_type_rr_ri<string OpcStr> {
|
||||
defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
|
||||
defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
|
||||
defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
|
||||
defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
|
||||
defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
|
||||
defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
|
||||
}
|
||||
|
||||
// Multiclass for EQ.
|
||||
multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
|
||||
defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
|
||||
defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
|
||||
defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
|
||||
defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
|
||||
}
|
||||
|
||||
// Multiclass for GTU.
|
||||
multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
|
||||
defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
|
||||
defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
|
||||
defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
|
||||
defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
|
||||
defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
|
||||
defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
|
||||
}
|
||||
|
||||
// Multiclass for tstbit.
|
||||
multiclass NVJ_type_r0<string OpcStr> {
|
||||
defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
|
||||
defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
|
||||
}
|
||||
|
||||
// Base Multiclass for New Value Jump.
|
||||
multiclass NVJ_type {
|
||||
defm GT : NVJ_type_rr_ri<"cmp.gt">;
|
||||
defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
|
||||
defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
|
||||
defm TSTBIT : NVJ_type_r0<"tstbit">;
|
||||
}
|
||||
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
defm JMP_ : NVJ_type;
|
||||
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
|
||||
Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
|
||||
defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
|
||||
defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
|
||||
defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
|
||||
defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
|
||||
defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// NV/J -
|
||||
// multiclass/template class for the new-value compare jumps instruction
|
||||
// with a register and an unsigned immediate (U5) operand.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
|
||||
class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
|
||||
bit isTaken>
|
||||
: NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
|
||||
"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
|
||||
#!if(isTaken, "t","nt")#" $offset",
|
||||
[]>, Requires<[HasV4T]> {
|
||||
|
||||
let isPredicatedFalse = isNegCond;
|
||||
let isBrTaken = !if(isTaken, "true", "false");
|
||||
|
||||
bits<3> src1;
|
||||
bits<5> src2;
|
||||
bits<11> offset;
|
||||
|
||||
let IClass = 0b0010;
|
||||
let Inst{26} = 0b1;
|
||||
let Inst{25-23} = majOp;
|
||||
let Inst{22} = isNegCond;
|
||||
let Inst{18-16} = src1;
|
||||
let Inst{13} = isTaken;
|
||||
let Inst{12-8} = src2;
|
||||
let Inst{21-20} = offset{10-9};
|
||||
let Inst{7-1} = offset{8-2};
|
||||
}
|
||||
|
||||
multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
|
||||
// Branch not taken:
|
||||
def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
|
||||
// Branch taken:
|
||||
def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
|
||||
}
|
||||
|
||||
multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
|
||||
let BaseOpcode = BaseOp#_NVJri in {
|
||||
defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
|
||||
defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
|
||||
}
|
||||
}
|
||||
|
||||
// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
|
||||
|
||||
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
|
||||
Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
|
||||
defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
|
||||
defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
|
||||
defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// multiclass/template class for the new-value compare jumps instruction
|
||||
// with a register and an hardcoded 0/-1 immediate value.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
|
||||
class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
|
||||
bit isNegCond, bit isTaken>
|
||||
: NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, brtarget:$offset),
|
||||
"if ("#!if(isNegCond, "!","")#mnemonic
|
||||
#"($src1.new, #"#ImmVal#")) jump:"
|
||||
#!if(isTaken, "t","nt")#" $offset",
|
||||
[]>, Requires<[HasV4T]> {
|
||||
|
||||
let isPredicatedFalse = isNegCond;
|
||||
let isBrTaken = !if(isTaken, "true", "false");
|
||||
|
||||
bits<3> src1;
|
||||
bits<11> offset;
|
||||
let IClass = 0b0010;
|
||||
let Inst{26} = 0b1;
|
||||
let Inst{25-23} = majOp;
|
||||
let Inst{22} = isNegCond;
|
||||
let Inst{18-16} = src1;
|
||||
let Inst{13} = isTaken;
|
||||
let Inst{21-20} = offset{10-9};
|
||||
let Inst{7-1} = offset{8-2};
|
||||
}
|
||||
|
||||
multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
|
||||
bit isNegCond> {
|
||||
// Branch not taken:
|
||||
def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
|
||||
// Branch taken:
|
||||
def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
|
||||
}
|
||||
|
||||
multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
|
||||
string ImmVal> {
|
||||
let BaseOpcode = BaseOp#_NVJ_ConstImm in {
|
||||
defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
|
||||
defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
|
||||
}
|
||||
}
|
||||
|
||||
// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
|
||||
// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
|
||||
|
||||
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
|
||||
Defs = [PC], neverHasSideEffects = 1 in {
|
||||
defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
|
||||
defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
|
||||
defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XTYPE/ALU +
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -3007,9 +3021,10 @@ def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
|
||||
|
||||
|
||||
// Transfer global address into a register
|
||||
let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
|
||||
def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
|
||||
"$dst = ##$src1",
|
||||
let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
|
||||
isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
|
||||
def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
|
||||
"$dst = #$src1",
|
||||
[(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
@ -22,29 +22,31 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
#define DEBUG_TYPE "hexagon-nvj"
|
||||
#include "Hexagon.h"
|
||||
#include "HexagonInstrInfo.h"
|
||||
#include "HexagonMachineFunctionInfo.h"
|
||||
#include "HexagonRegisterInfo.h"
|
||||
#include "HexagonSubtarget.h"
|
||||
#include "HexagonTargetMachine.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/CodeGen/LiveVariables.h"
|
||||
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
|
||||
#include "llvm/PassSupport.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/LiveVariables.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "Hexagon.h"
|
||||
#include "HexagonTargetMachine.h"
|
||||
#include "HexagonRegisterInfo.h"
|
||||
#include "HexagonSubtarget.h"
|
||||
#include "HexagonInstrInfo.h"
|
||||
#include "HexagonMachineFunctionInfo.h"
|
||||
|
||||
#include <map>
|
||||
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
using namespace llvm;
|
||||
|
||||
STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
|
||||
@ -57,6 +59,11 @@ static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
|
||||
cl::ZeroOrMore, cl::init(false),
|
||||
cl::desc("Disable New Value Jumps"));
|
||||
|
||||
namespace llvm {
|
||||
void initializeHexagonNewValueJumpPass(PassRegistry&);
|
||||
}
|
||||
|
||||
|
||||
namespace {
|
||||
struct HexagonNewValueJump : public MachineFunctionPass {
|
||||
const HexagonInstrInfo *QII;
|
||||
@ -65,7 +72,9 @@ namespace {
|
||||
public:
|
||||
static char ID;
|
||||
|
||||
HexagonNewValueJump() : MachineFunctionPass(ID) { }
|
||||
HexagonNewValueJump() : MachineFunctionPass(ID) {
|
||||
initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
AU.addRequired<MachineBranchProbabilityInfo>();
|
||||
@ -88,6 +97,13 @@ namespace {
|
||||
|
||||
char HexagonNewValueJump::ID = 0;
|
||||
|
||||
INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
|
||||
"Hexagon NewValueJump", false, false)
|
||||
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
|
||||
INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
|
||||
"Hexagon NewValueJump", false, false)
|
||||
|
||||
|
||||
// We have identified this II could be feeder to NVJ,
|
||||
// verify that it can be.
|
||||
static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
|
||||
@ -219,7 +235,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned cmpReg1, cmpOp2;
|
||||
unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
|
||||
cmpReg1 = MI->getOperand(1).getReg();
|
||||
|
||||
if (secondReg) {
|
||||
@ -285,43 +301,48 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
|
||||
|
||||
switch (MI->getOpcode()) {
|
||||
case Hexagon::CMPEQrr:
|
||||
return taken ? Hexagon::JMP_EQrrPt_nv_V4 : Hexagon::JMP_EQrrPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPEQrr_t_Jumpnv_nt_V4;
|
||||
|
||||
case Hexagon::CMPEQri: {
|
||||
if (reg >= 0)
|
||||
return taken ? Hexagon::JMP_EQriPt_nv_V4 : Hexagon::JMP_EQriPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPEQri_t_Jumpnv_nt_V4;
|
||||
else
|
||||
return taken ? Hexagon::JMP_EQriPtneg_nv_V4
|
||||
: Hexagon::JMP_EQriPntneg_nv_V4;
|
||||
return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPEQn1_t_Jumpnv_nt_V4;
|
||||
}
|
||||
|
||||
case Hexagon::CMPGTrr: {
|
||||
if (secondRegNewified)
|
||||
return taken ? Hexagon::JMP_GTrrdnPt_nv_V4
|
||||
: Hexagon::JMP_GTrrdnPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPLTrr_t_Jumpnv_nt_V4;
|
||||
else
|
||||
return taken ? Hexagon::JMP_GTrrPt_nv_V4
|
||||
: Hexagon::JMP_GTrrPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPGTrr_t_Jumpnv_nt_V4;
|
||||
}
|
||||
|
||||
case Hexagon::CMPGTri: {
|
||||
if (reg >= 0)
|
||||
return taken ? Hexagon::JMP_GTriPt_nv_V4 : Hexagon::JMP_GTriPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPGTri_t_Jumpnv_nt_V4;
|
||||
else
|
||||
return taken ? Hexagon::JMP_GTriPtneg_nv_V4
|
||||
: Hexagon::JMP_GTriPntneg_nv_V4;
|
||||
return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPGTn1_t_Jumpnv_nt_V4;
|
||||
}
|
||||
|
||||
case Hexagon::CMPGTUrr: {
|
||||
if (secondRegNewified)
|
||||
return taken ? Hexagon::JMP_GTUrrdnPt_nv_V4
|
||||
: Hexagon::JMP_GTUrrdnPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPLTUrr_t_Jumpnv_nt_V4;
|
||||
else
|
||||
return taken ? Hexagon::JMP_GTUrrPt_nv_V4 : Hexagon::JMP_GTUrrPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPGTUrr_t_Jumpnv_nt_V4;
|
||||
}
|
||||
|
||||
case Hexagon::CMPGTUri:
|
||||
return taken ? Hexagon::JMP_GTUriPt_nv_V4 : Hexagon::JMP_GTUriPnt_nv_V4;
|
||||
return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4
|
||||
: Hexagon::CMPGTUri_t_Jumpnv_nt_V4;
|
||||
|
||||
default:
|
||||
llvm_unreachable("Could not find matching New Value Jump instruction.");
|
||||
|
||||
@ -2774,9 +2774,8 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
|
||||
// If an instruction feeds new value jump, glue it.
|
||||
MachineBasicBlock::iterator NextMII = I;
|
||||
++NextMII;
|
||||
MachineInstr *NextMI = NextMII;
|
||||
|
||||
if (QII->isNewValueJump(NextMI)) {
|
||||
if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
|
||||
MachineInstr *NextMI = NextMII;
|
||||
|
||||
bool secondRegMatch = false;
|
||||
bool maintainNewValueJump = false;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user