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Fix Intel asm syntax for the bsr and bsf instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45030 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -450,32 +450,32 @@ def XCHG32rm : I<0x87, MRMSrcMem,
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF16rr : I<0xBC, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
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"bsf{w}\t{$src, $dst||$dst, $src}",
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"bsf{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
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def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsf{w}\t{$src, $dst||$dst, $src}",
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"bsf{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
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(implicit EFLAGS)]>, TB;
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def BSF32rr : I<0xBC, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
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"bsf{l}\t{$src, $dst||$dst, $src}",
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"bsf{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
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def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsf{l}\t{$src, $dst||$dst, $src}",
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"bsf{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
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(implicit EFLAGS)]>, TB;
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def BSR16rr : I<0xBD, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
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"bsr{w}\t{$src, $dst||$dst, $src}",
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"bsr{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
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def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsr{w}\t{$src, $dst||$dst, $src}",
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"bsr{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
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(implicit EFLAGS)]>, TB;
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def BSR32rr : I<0xBD, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
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"bsr{l}\t{$src, $dst||$dst, $src}",
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"bsr{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
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def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsr{l}\t{$src, $dst||$dst, $src}",
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"bsr{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
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(implicit EFLAGS)]>, TB;
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} // Defs = [EFLAGS]
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@ -170,17 +170,17 @@ def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF64rr : RI<0xBC, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bsf{q}\t{$src, $dst||$dst, $src}",
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf GR64:$src))]>, TB;
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def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsf{q}\t{$src, $dst||$dst, $src}",
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf (loadi64 addr:$src)))]>, TB;
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def BSR64rr : RI<0xBD, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bsr{q}\t{$src, $dst||$dst, $src}",
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr GR64:$src))]>, TB;
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def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsr{q}\t{$src, $dst||$dst, $src}",
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr (loadi64 addr:$src)))]>, TB;
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} // Defs = [EFLAGS]
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