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AArch64: support f16 extend/trunc operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -305,6 +305,7 @@ AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
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// AArch64 does not have floating-point extending loads, i1 sign-extending
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// load, floating-point truncating stores, or v2i32->v2i16 truncating store.
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setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
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@ -24,3 +24,39 @@ define void @test_bitcast_to_half(half* %addr, i16 %in) {
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store half %val_fp, half* %addr
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ret void
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}
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define float @test_extend32(half* %addr) {
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; CHECK-LABEL: test_extend32:
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; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
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%val16 = load half* %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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}
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define double @test_extend64(half* %addr) {
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; CHECK-LABEL: test_extend64:
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; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
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%val16 = load half* %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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}
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define void @test_trunc32(float %in, half* %addr) {
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; CHECK-LABEL: test_trunc32:
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; CHECK: fcvt {{h[0-9]+}}, {{s[0-9]+}}
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%val16 = fptrunc float %in to half
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store half %val16, half* %addr
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ret void
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}
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define void @test_trunc64(double %in, half* %addr) {
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; CHECK-LABEL: test_trunc64:
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; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}}
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%val16 = fptrunc double %in to half
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store half %val16, half* %addr
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ret void
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}
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