From 1a9f21abac47dcea0c62341b0ee4fd35481350b8 Mon Sep 17 00:00:00 2001
From: Mihai Popa <mihail.popa@gmail.com>
Date: Wed, 21 Aug 2013 13:14:58 +0000
Subject: [PATCH] Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/ARM/ARMInstrInfo.td | 5 +++++
lib/Target/ARM/ARMInstrThumb2.td | 3 +++
lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 9 +++++++++
test/MC/ARM/basic-thumb2-instructions.s | 17 ++++++++++++++++-
4 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 280757fb37d..3b836671ce3 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -710,6 +710,11 @@ def imm0_65535_expr : Operand<i32> {
let ParserMatchClass = Imm0_65535ExprAsmOperand;
}
+def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
+def imm256_65535_expr : Operand<i32> {
+ let ParserMatchClass = Imm256_65535ExprAsmOperand;
+}
+
/// imm24b - True if the 32-bit immediate is encodable in 24 bits.
def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
def imm24b : Operand<i32>, ImmLeaf<i32, [{
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 02ff08bb47c..3498e41ba1b 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1855,6 +1855,9 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
let DecoderMethod = "DecodeT2MOVTWInstruction";
}
+def : t2InstAlias<"mov${p} $Rd, $imm",
+ (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
+
def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index df9306a9b99..7467071db32 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -867,6 +867,15 @@ public:
int64_t Value = CE->getValue();
return Value >= 0 && Value < 65536;
}
+ bool isImm256_65535Expr() const {
+ if (!isImm()) return false;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ // If it's not a constant expression, it'll generate a fixup and be
+ // handled later.
+ if (!CE) return true;
+ int64_t Value = CE->getValue();
+ return Value >= 256 && Value < 65536;
+ }
bool isImm0_65535Expr() const {
if (!isImm()) return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 59318aa16d1..73ed46bd0ce 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -1323,8 +1323,15 @@ _func:
movlo r1, #-1
@ alias for mvn
- mov r3, #-3
+ mov r3, #-3
+ mov r11, #0xabcd
+ movs r0, #1
+ it ne
+ movne r3, #15
+ itt eq
+ moveq r0, #255
+ moveq r1, #256
@ CHECK: movs r1, #21 @ encoding: [0x15,0x21]
@ CHECK: movs.w r1, #21 @ encoding: [0x5f,0xf0,0x15,0x01]
@@ -1343,6 +1350,14 @@ _func:
@ CHECK: it lo @ encoding: [0x38,0xbf]
@ CHECK: movlo.w r1, #-1 @ encoding: [0x4f,0xf0,0xff,0x31]
@ CHECK: mvn r3, #2 @ encoding: [0x6f,0xf0,0x02,0x03]
+@ CHECK: movw r11, #43981 @ encoding: [0x4a,0xf6,0xcd,0x3b]
+@ CHECK: movs r0, #1 @ encoding: [0x01,0x20]
+@ CHECK: it ne @ encoding: [0x18,0xbf]
+@ CHECK: movne r3, #15 @ encoding: [0x0f,0x23]
+
+@ CHECK: itt eq @ encoding: [0x04,0xbf]
+@ CHECK: moveq r0, #255 @ encoding: [0xff,0x20]
+@ CHECK: movweq r1, #256 @ encoding: [0x40,0xf2,0x00,0x11]
@------------------------------------------------------------------------------
@ MOV(shifted register)