From 1abf0afdd4d8e9d58518a878f30b9eede81303cc Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Sat, 7 Sep 2013 00:18:01 +0000 Subject: [PATCH] [mips] Add definition of instruction "drotr32" (double rotate right plus 32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 4 ++++ lib/Target/Mips/Mips64InstrInfo.td | 1 + test/MC/Mips/mips64-alu-instructions.s | 6 +++++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 02e93b8ddf6..3dfe428abf2 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -155,6 +155,9 @@ static void LowerLargeShift(MCInst& Inst) { case Mips::DSRA: Inst.setOpcode(Mips::DSRA32); return; + case Mips::DROTR: + Inst.setOpcode(Mips::DROTR32); + return; } } @@ -206,6 +209,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, case Mips::DSLL: case Mips::DSRL: case Mips::DSRA: + case Mips::DROTR: LowerLargeShift(TmpInst); break; // Double extract instruction is chosen by pos and size operands diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index f4e10747d93..b6a4f726a44 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -111,6 +111,7 @@ let Predicates = [HasMips64r2, HasStdEnc] in { SRA_FM<0x3a, 1>; def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>, SRLV_FM<0x16, 1>; + def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>; } /// Load and Store Instructions diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index c33ba70e2ca..8262a46ee4f 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for arithmetic and logical instructions. #------------------------------------------------------------------------------ @@ -73,6 +73,8 @@ # CHECK: daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64] # CHECK: daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65] # CHECK: daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00] +# CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] +# CHECK: drotr32 $9, $6, 52 # encoding: [0x3e,0x4d,0x26,0x00] # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] # CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] @@ -94,6 +96,8 @@ daddiu $9,$6,-15001 daddiu $9,-15001 daddu $9,$6,$7 + drotr $9, $6, 20 + drotr32 $9, $6, 52 madd $6,$7 maddu $6,$7 msub $6,$7