6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

ARM: Fix encoding of hint instruction for Thumb.

Browse Source 
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.

Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.

This commit adds a proper diagnostic message for Imm0_4 and updates all tests.

Patch by Mihail Popa <Mihail.Popa@arm.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
2013-04-26 17:54:54 +00:00
parent 140536b936
commit 1ad3a410be
10 changed files with 59 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@@ -1953,10 +1953,12 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Inst.addOperand(MCOperand::CreateImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::t2CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
S = MCDisassembler::SoftFail;
// imod == '00' && M == '0' --> this is a HINT instruction
int imm = fieldFromInstruction(Insn, 0, 8);
// HINT are defined only for immediate in [0..4]
if(imm > 4) return MCDisassembler::Fail;
Inst.setOpcode(ARM::t2HINT);
Inst.addOperand(MCOperand::CreateImm(imm));
}
return S;