From 1af0c40934f5b08772213aad2e99638330f5cf81 Mon Sep 17 00:00:00 2001 From: Renato Golin Date: Thu, 28 May 2015 12:10:37 +0000 Subject: [PATCH] [ARMTargetParser] Adding a few more CPUs for Clang CPU detection. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238415 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Support/TargetParser.h | 4 ++-- lib/Support/TargetParser.cpp | 36 ++++++++++++++++++----------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/include/llvm/Support/TargetParser.h b/include/llvm/Support/TargetParser.h index 9bd4b45bd92..fd32c25f5c2 100644 --- a/include/llvm/Support/TargetParser.h +++ b/include/llvm/Support/TargetParser.h @@ -53,7 +53,6 @@ namespace ARM { AK_ARMV3M, AK_ARMV4, AK_ARMV4T, - AK_ARMV5, AK_ARMV5T, AK_ARMV5TE, AK_ARMV5TEJ, @@ -64,7 +63,6 @@ namespace ARM { AK_ARMV6ZK, AK_ARMV6M, AK_ARMV6SM, - AK_ARMV7, AK_ARMV7A, AK_ARMV7R, AK_ARMV7M, @@ -75,9 +73,11 @@ namespace ARM { AK_IWMMXT, AK_IWMMXT2, AK_XSCALE, + AK_ARMV5, AK_ARMV5E, AK_ARMV6J, AK_ARMV6HL, + AK_ARMV7, AK_ARMV7L, AK_ARMV7HL, AK_ARMV7S, diff --git a/lib/Support/TargetParser.cpp b/lib/Support/TargetParser.cpp index 48329b2a69f..93bf9ae5761 100644 --- a/lib/Support/TargetParser.cpp +++ b/lib/Support/TargetParser.cpp @@ -61,7 +61,6 @@ struct { { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::Pre_v4 }, { "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 }, { "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T }, - { "armv5", ARM::AK_ARMV5, "5T", ARMBuildAttrs::CPUArch::v5T }, { "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T }, { "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE }, { "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", ARMBuildAttrs::CPUArch::v5TEJ }, @@ -72,7 +71,6 @@ struct { { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ }, { "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M }, { "armv6s-m", ARM::AK_ARMV6SM, "6S-M", ARMBuildAttrs::CPUArch::v6S_M }, - { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 }, { "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 }, { "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 }, { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 }, @@ -83,9 +81,11 @@ struct { { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE }, { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }, { "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE }, + { "armv5", ARM::AK_ARMV5, "5T", ARMBuildAttrs::CPUArch::v5T }, { "armv5e", ARM::AK_ARMV5E, "5TE", ARMBuildAttrs::CPUArch::v5TE }, { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 }, { "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M }, + { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 }, { "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 }, { "armv7hl", ARM::AK_ARMV7HL, "7-L", ARMBuildAttrs::CPUArch::v7 }, { "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 } @@ -108,6 +108,7 @@ struct { // List of CPU names and their arches. // The same CPU can have multiple arches and can be default on multiple arches. // When finding the Arch for a CPU, first-found prevails. Sort them accordingly. +// When this becomes table-generated, we'd probably need two tables. // FIXME: TableGen this. struct { const char *Name; @@ -115,9 +116,15 @@ struct { bool Default; } CPUNames[] = { { "arm2", ARM::AK_ARMV2, true }, + { "arm3", ARM::AK_ARMV2A, true }, { "arm6", ARM::AK_ARMV3, true }, { "arm7m", ARM::AK_ARMV3M, true }, + { "arm8", ARM::AK_ARMV4, false }, + { "arm810", ARM::AK_ARMV4, false }, { "strongarm", ARM::AK_ARMV4, true }, + { "strongarm110", ARM::AK_ARMV4, false }, + { "strongarm1100", ARM::AK_ARMV4, false }, + { "strongarm1110", ARM::AK_ARMV4, false }, { "arm7tdmi", ARM::AK_ARMV4T, true }, { "arm7tdmi-s", ARM::AK_ARMV4T, false }, { "arm710t", ARM::AK_ARMV4T, false }, @@ -130,24 +137,21 @@ struct { { "arm9312", ARM::AK_ARMV4T, false }, { "arm940t", ARM::AK_ARMV4T, false }, { "ep9312", ARM::AK_ARMV4T, false }, - { "arm10tdmi", ARM::AK_ARMV5, true }, { "arm10tdmi", ARM::AK_ARMV5T, true }, { "arm1020t", ARM::AK_ARMV5T, false }, - { "xscale", ARM::AK_XSCALE, true }, - { "xscale", ARM::AK_ARMV5TE, false }, { "arm9e", ARM::AK_ARMV5TE, false }, - { "arm926ej-s", ARM::AK_ARMV5TE, false }, - { "arm946ej-s", ARM::AK_ARMV5TE, false }, + { "arm946e-s", ARM::AK_ARMV5TE, false }, { "arm966e-s", ARM::AK_ARMV5TE, false }, { "arm968e-s", ARM::AK_ARMV5TE, false }, + { "arm10e", ARM::AK_ARMV5TE, false }, { "arm1020e", ARM::AK_ARMV5TE, false }, { "arm1022e", ARM::AK_ARMV5TE, true }, { "iwmmxt", ARM::AK_ARMV5TE, false }, - { "iwmmxt", ARM::AK_IWMMXT, true }, + { "xscale", ARM::AK_ARMV5TE, false }, + { "arm926ej-s", ARM::AK_ARMV5TEJ, true }, { "arm1136jf-s", ARM::AK_ARMV6, true }, - { "arm1136j-s", ARM::AK_ARMV6J, true }, - { "arm1136jz-s", ARM::AK_ARMV6J, false }, { "arm1176j-s", ARM::AK_ARMV6K, false }, + { "arm1176jz-s", ARM::AK_ARMV6K, false }, { "mpcore", ARM::AK_ARMV6K, false }, { "mpcorenovfp", ARM::AK_ARMV6K, false }, { "arm1176jzf-s", ARM::AK_ARMV6K, true }, @@ -159,7 +163,6 @@ struct { { "cortex-m0plus", ARM::AK_ARMV6M, false }, { "cortex-m1", ARM::AK_ARMV6M, false }, { "sc000", ARM::AK_ARMV6M, false }, - { "cortex-a8", ARM::AK_ARMV7, true }, { "cortex-a5", ARM::AK_ARMV7A, false }, { "cortex-a7", ARM::AK_ARMV7A, false }, { "cortex-a8", ARM::AK_ARMV7A, true }, @@ -174,18 +177,23 @@ struct { { "cortex-r7", ARM::AK_ARMV7R, false }, { "sc300", ARM::AK_ARMV7M, false }, { "cortex-m3", ARM::AK_ARMV7M, true }, - { "cortex-m4", ARM::AK_ARMV7M, false }, - { "cortex-m7", ARM::AK_ARMV7M, false }, + { "cortex-m4", ARM::AK_ARMV7EM, true }, + { "cortex-m7", ARM::AK_ARMV7EM, false }, { "cortex-a53", ARM::AK_ARMV8A, true }, { "cortex-a57", ARM::AK_ARMV8A, false }, { "cortex-a72", ARM::AK_ARMV8A, false }, { "cyclone", ARM::AK_ARMV8A, false }, { "generic", ARM::AK_ARMV8_1A, true }, // Non-standard Arch names. + { "iwmmxt", ARM::AK_IWMMXT, true }, + { "xscale", ARM::AK_XSCALE, true }, + { "arm10tdmi", ARM::AK_ARMV5, true }, { "arm1022e", ARM::AK_ARMV5E, true }, - { "arm926ej-s", ARM::AK_ARMV5TEJ, true }, + { "arm1136j-s", ARM::AK_ARMV6J, true }, + { "arm1136jz-s", ARM::AK_ARMV6J, false }, { "cortex-m0", ARM::AK_ARMV6SM, true }, { "arm1176jzf-s", ARM::AK_ARMV6HL, true }, + { "cortex-a8", ARM::AK_ARMV7, true }, { "cortex-a8", ARM::AK_ARMV7L, true }, { "cortex-a8", ARM::AK_ARMV7HL, true }, { "cortex-m4", ARM::AK_ARMV7EM, true },