6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-17 20:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Note that ADDC and company don't actually expand yet (missing in legalize

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2008-10-07 02:10:26 +00:00
parent e4a4245906
commit 1b19ef0295
4 changed files with 65 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/llvm/Intrinsics.td
View File

@ -360,3 +360,4 @@ include "llvm/IntrinsicsPowerPC.td"
include "llvm/IntrinsicsX86.td"
include "llvm/IntrinsicsARM.td"
include "llvm/IntrinsicsCellSPU.td"
include "llvm/IntrinsicsAlpha.td"

19
include/llvm/IntrinsicsAlpha.td Normal file
View File

@ -0,0 +1,19 @@
//===- IntrinsicsAlpha.td - Defines Alpha intrinsics -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines all of the Alpha-specific intrinsics.
//
//===----------------------------------------------------------------------===//
let TargetPrefix = "alpha" in { // All intrinsics start with "llvm.alpha.".
def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">,
Intrinsic<[llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
}

3
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -323,7 +323,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP: {
case ISD::TargetConstantFP:
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
bool isDouble = N->getValueType(0) == MVT::f64;
MVT T = isDouble ? MVT::f64 : MVT::f32;

44
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/Module.h"
#include "llvm/Intrinsics.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
@ -47,7 +48,10 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
@ -87,6 +91,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::SDIV , MVT::i64, Custom);
setOperationAction(ISD::UDIV , MVT::i64, Custom);
setOperationAction(ISD::ADDC , MVT::i64, Expand);
setOperationAction(ISD::ADDE , MVT::i64, Expand);
setOperationAction(ISD::SUBC , MVT::i64, Expand);
setOperationAction(ISD::SUBE , MVT::i64, Expand);
// We don't support sin/cos/sqrt/pow
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
@ -311,6 +321,29 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
break;
}
case 5: {
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg1, ArgReg2;
if (ArgVT.isInteger()) {
ArgReg1 = Alpha::R0;
ArgReg2 = Alpha::R1;
} else {
assert(ArgVT.isFloatingPoint());
ArgReg1 = Alpha::F0;
ArgReg2 = Alpha::F1;
}
Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
break;
}
}
return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
@ -432,6 +465,15 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::RET: return LowerRET(Op,DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2));
}
}
case ISD::SINT_TO_FP: {
assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");