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When verifying two-address instructions, check the following:
- Kill is implicit when use and def registers are identical. - Only virtual registers can differ. Add a -verify-fast-regalloc to run the verifier before the fast allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103797 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -47,7 +47,7 @@ namespace {
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MachineVerifier(Pass *pass, bool allowDoubleDefs) :
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PASS(pass),
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allowVirtDoubleDefs(allowDoubleDefs),
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allowPhysDoubleDefs(allowDoubleDefs),
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allowPhysDoubleDefs(true),
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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
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{}
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@ -552,19 +552,23 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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regsLiveInButUnused.erase(Reg);
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bool isKill = false;
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if (MO->isKill()) {
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isKill = true;
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// Tied operands on two-address instuctions MUST NOT have a <kill> flag.
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if (MI->isRegTiedToDefOperand(MONum))
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unsigned defIdx;
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if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
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// A two-addr use counts as a kill if use and def are the same.
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unsigned DefReg = MI->getOperand(defIdx).getReg();
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if (Reg == DefReg) {
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isKill = true;
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// ANd in that case an explicit kill flag is not allowed.
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if (MO->isKill())
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report("Illegal kill flag on two-address instruction operand",
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MO, MONum);
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} else {
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// TwoAddress instr modifying a reg is treated as kill+def.
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unsigned defIdx;
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if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
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MI->getOperand(defIdx).getReg() == Reg)
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isKill = true;
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}
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} else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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report("Two-address instruction operands must be identical",
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MO, MONum);
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}
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} else
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isKill = MO->isKill();
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if (isKill) {
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addRegWithSubRegs(regsKilled, Reg);
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@ -35,6 +35,9 @@
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#include <algorithm>
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using namespace llvm;
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static cl::opt<bool> VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden,
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cl::desc("Verify machine code before fast regalloc"));
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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@ -778,6 +781,8 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
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DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
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<< "********** Function: "
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<< ((Value*)Fn.getFunction())->getName() << '\n');
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if (VerifyFastRegalloc)
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Fn.verify();
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MF = &Fn;
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MRI = &MF->getRegInfo();
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TM = &Fn.getTarget();
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