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Thumb MUL assembly parsing for 3-operand form.

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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-11-10 22:10:12 +00:00
parent eaf4221cef
commit 1b332860ae
2 changed files with 11 additions and 7 deletions
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16
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -3415,13 +3415,15 @@ cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
} }
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
((ARMOperand*)Operands[4])->addRegOperands(Inst, 1); // If we have a three-operand form, make sure to set Rn to be the operand
// If we have a three-operand form, use that, else the second source operand // that isn't the same as Rd.
// is just the destination operand again. unsigned RegOp = 4;
if (Operands.size() == 6) if (Operands.size() == 6 &&
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[4])->getReg() ==
else ((ARMOperand*)Operands[3])->getReg())
Inst.addOperand(Inst.getOperand(0)); RegOp = 5;
((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
Inst.addOperand(Inst.getOperand(0));
((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
return true; return true;

2
test/MC/ARM/basic-thumb-instructions.s
View File

@@ -372,9 +372,11 @@ _func:
@ MUL @ MUL
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
muls r1, r2, r1 muls r1, r2, r1
muls r2, r2, r3
muls r3, r4 muls r3, r4
@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43] @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
@ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]