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Revert 110491. While not wrong, it was based on a
misanalysis and is undesirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1206,36 +1206,31 @@ let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
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"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
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}
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multiclass sse12_cmp_scalar_int<RegisterClass RC, Operand memopr,
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ComplexPattern mem_cpat, Intrinsic Int, string asm> {
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multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
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Intrinsic Int, string asm> {
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def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
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[(set VR128:$dst, (Int VR128:$src1,
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VR128:$src, imm:$cc))]>;
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def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memopr:$src, SSECC:$cc), asm,
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(ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
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[(set VR128:$dst, (Int VR128:$src1,
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mem_cpat:$src, imm:$cc))]>;
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(load addr:$src), imm:$cc))]>;
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}
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// Aliases to match intrinsics which expect XMM operand(s).
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let isAsmParserOnly = 1 in {
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defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
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int_x86_sse_cmp_ss,
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defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
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"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
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XS, VEX_4V;
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defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
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int_x86_sse2_cmp_sd,
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defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
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"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
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XD, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm Int_CMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
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int_x86_sse_cmp_ss,
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defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
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"cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
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defm Int_CMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
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int_x86_sse2_cmp_sd,
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defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
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"cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
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}
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@ -1,27 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-applecl-darwin11 | FileCheck %s
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; 8193553
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define void @__math_kernel_Vectorized_wrapper(<4 x double> addrspace(1)* %a, <4 x double> addrspace(1)* %b, i64 addrspace(1)* %c, i64 addrspace(1)* %d) nounwind {
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entry.i: ; preds = %entry.i, %loop
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; CHECK: math_kernel_Vectorized_wrapper
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; CHECK-NOT: cmpordsd (%rsi),
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%0 = alloca i8
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%1 = alloca i8
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%2 = alloca i8
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%tmp213.i = load <4 x double> addrspace(1)* %a ; <<4 x double>> [#uses=4]
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%extract25.i = extractelement <4 x double> %tmp213.i, i32 1 ; <double> [#uses=1]
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%tmp723.i = load <4 x double> addrspace(1)* %b ; <<4 x double>> [#uses=4]
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%extract29.i = extractelement <4 x double> %tmp723.i, i32 1 ; <double> [#uses=1]
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%tmp2.i26 = insertelement <2 x double> undef, double %extract25.i, i32 0 ; <<2 x double>> [#uses=1]
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%tmp5.i27 = insertelement <2 x double> undef, double %extract29.i, i32 1 ; <<2 x double>> [#uses=1]
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%cmpsd.i.i28 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %tmp2.i26, <2 x double> %tmp5.i27, i8 7) nounwind ; <<2 x double>> [#uses=1]
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%3 = bitcast <2 x double> %cmpsd.i.i28 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp12.i29 = extractelement <4 x i32> %3, i32 0 ; <i32> [#uses=1]
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%and.i30 = and i32 %tmp12.i29, 1 ; <i32> [#uses=1]
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%conv937.i36 = zext i32 %and.i30 to i64 ; <i64> [#uses=1]
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store i64 %conv937.i36, i64 addrspace(1)* %d
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ret void
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; CHECK: ret
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}
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declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
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