From 1b7371331fef3db77999b9c4ca62c2ddbaf1d804 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 8 May 2006 17:22:53 +0000 Subject: [PATCH] When tracking demanded bits, if any bits from the sext of an SRA are demanded, then so is the input sign bit. This fixes mediabench/g721 on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28166 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 41405408de5..bbe8e95b785 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -467,8 +467,14 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, HighBits <<= MVT::getSizeInBits(VT) - ShAmt; uint64_t TypeMask = MVT::getIntVTBitMask(VT); - if (SimplifyDemandedBits(Op.getOperand(0), - (DemandedMask << ShAmt) & TypeMask, + uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; + + // If any of the demanded bits are produced by the sign extension, we also + // demand the input sign bit. + if (HighBits & DemandedMask) + InDemandedMask |= MVT::getIntVTSignBit(VT); + + if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, TLO, Depth+1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");