mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
PTX: Rename register classes for readability and combine int and fp registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
79c890f64f
commit
1b91bcddd5
@ -79,12 +79,12 @@ static const char PARAM_PREFIX[] = "__param_";
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static const char *getRegisterTypeName(unsigned RegNo) {
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#define TEST_REGCLS(cls, clsstr) \
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if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
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TEST_REGCLS(Preds, pred);
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TEST_REGCLS(RRegu16, u16);
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TEST_REGCLS(RRegu32, u32);
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TEST_REGCLS(RRegu64, u64);
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TEST_REGCLS(RRegf32, f32);
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TEST_REGCLS(RRegf64, f64);
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TEST_REGCLS(RegPred, pred);
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TEST_REGCLS(RegI16, u16);
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TEST_REGCLS(RegI32, u32);
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TEST_REGCLS(RegI64, u64);
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TEST_REGCLS(RegF32, f32);
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TEST_REGCLS(RegF64, f64);
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#undef TEST_REGCLS
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llvm_unreachable("Not in any register class!");
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@ -27,12 +27,12 @@ using namespace llvm;
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PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Set up the register classes.
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addRegisterClass(MVT::i1, PTX::PredsRegisterClass);
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addRegisterClass(MVT::i16, PTX::RRegu16RegisterClass);
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addRegisterClass(MVT::i32, PTX::RRegu32RegisterClass);
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addRegisterClass(MVT::i64, PTX::RRegu64RegisterClass);
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addRegisterClass(MVT::f32, PTX::RRegf32RegisterClass);
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addRegisterClass(MVT::f64, PTX::RRegf64RegisterClass);
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addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
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addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
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addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
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addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
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addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
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addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
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setBooleanContents(ZeroOrOneBooleanContent);
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@ -63,7 +63,7 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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// need to lower SETCC of Preds into bitwise logic
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// need to lower SETCC of RegPred into bitwise logic
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setOperationAction(ISD::SETCC, MVT::i1, Custom);
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setMinFunctionAlignment(2);
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@ -161,12 +161,12 @@ struct argmap_entry {
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void reset() { loc = RC->begin(); }
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bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
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} argmap[] = {
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argmap_entry(MVT::i1, PTX::PredsRegisterClass),
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argmap_entry(MVT::i16, PTX::RRegu16RegisterClass),
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argmap_entry(MVT::i32, PTX::RRegu32RegisterClass),
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argmap_entry(MVT::i64, PTX::RRegu64RegisterClass),
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argmap_entry(MVT::f32, PTX::RRegf32RegisterClass),
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argmap_entry(MVT::f64, PTX::RRegf64RegisterClass)
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argmap_entry(MVT::i1, PTX::RegPredRegisterClass),
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argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
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argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
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argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
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argmap_entry(MVT::f32, PTX::RegF32RegisterClass),
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argmap_entry(MVT::f64, PTX::RegF64RegisterClass)
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};
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} // end anonymous namespace
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@ -212,7 +212,7 @@ SDValue PTXTargetLowering::
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if (entry == argmap + array_lengthof(argmap))
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llvm_unreachable("Type of argument is not supported");
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if (MFI->isKernel() && entry->RC == PTX::PredsRegisterClass)
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if (MFI->isKernel() && entry->RC == PTX::RegPredRegisterClass)
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llvm_unreachable("cannot pass preds to kernel");
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MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
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@ -277,11 +277,11 @@ SDValue PTXTargetLowering::
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reg = PTX::RD0;
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}
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else if (Outs[0].VT == MVT::f32) {
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reg = PTX::F0;
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reg = PTX::R0;
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}
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else {
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assert(Outs[0].VT == MVT::f64 && "Can return only basic types");
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reg = PTX::FD0;
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reg = PTX::RD0;
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}
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MachineFunction &MF = DAG.getMachineFunction();
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@ -9,7 +9,7 @@
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// PTX Predicate operand, default to (0, 0) = (zero-reg, always).
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// Leave PrintMethod empty; predicate printing is defined elsewhere.
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def pred : PredicateOperand<OtherVT, (ops Preds, i32imm),
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def pred : PredicateOperand<OtherVT, (ops RegPred, i32imm),
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(ops (i1 zero_reg), (i32 0))>;
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let Namespace = "PTX" in {
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@ -33,12 +33,12 @@ static const struct map_entry {
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const TargetRegisterClass *cls;
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const int opcode;
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} map[] = {
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{ &PTX::RRegu16RegClass, PTX::MOVU16rr },
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{ &PTX::RRegu32RegClass, PTX::MOVU32rr },
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{ &PTX::RRegu64RegClass, PTX::MOVU64rr },
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{ &PTX::RRegf32RegClass, PTX::MOVF32rr },
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{ &PTX::RRegf64RegClass, PTX::MOVF64rr },
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{ &PTX::PredsRegClass, PTX::MOVPREDrr }
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{ &PTX::RegI16RegClass, PTX::MOVU16rr },
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{ &PTX::RegI32RegClass, PTX::MOVU32rr },
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{ &PTX::RegI64RegClass, PTX::MOVU64rr },
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{ &PTX::RegF32RegClass, PTX::MOVF32rr },
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{ &PTX::RegF64RegClass, PTX::MOVF64rr },
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{ &PTX::RegPredRegClass, PTX::MOVPREDrr }
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};
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void PTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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@ -155,7 +155,7 @@ DefinesPredicate(MachineInstr *MI,
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const MachineOperand &MO = MI->getOperand(0);
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if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::PredsRegClass)
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if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass)
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return false;
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Pred.push_back(MO);
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File diff suppressed because it is too large
Load Diff
@ -14,14 +14,14 @@
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// PTX Special Purpose Register Accessor Intrinsics
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class PTX_READ_SPECIAL_REGISTER_R64<string regname, Intrinsic intop>
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: InstPTX<(outs RRegu64:$d), (ins),
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: InstPTX<(outs RegI64:$d), (ins),
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!strconcat("mov.u64\t$d, %", regname),
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[(set RRegu64:$d, (intop))]>;
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[(set RegI64:$d, (intop))]>;
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class PTX_READ_SPECIAL_REGISTER_R32<string regname, Intrinsic intop>
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: InstPTX<(outs RRegu32:$d), (ins),
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: InstPTX<(outs RegI32:$d), (ins),
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!strconcat("mov.u32\t$d, %", regname),
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[(set RRegu32:$d, (intop))]>;
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[(set RegI32:$d, (intop))]>;
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// TODO Add read vector-version of special registers
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@ -29,62 +29,6 @@ def P4 : PTXReg<"p4">;
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def P5 : PTXReg<"p5">;
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def P6 : PTXReg<"p6">;
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def P7 : PTXReg<"p7">;
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def P8 : PTXReg<"p8">;
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def P9 : PTXReg<"p9">;
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def P10 : PTXReg<"p10">;
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def P11 : PTXReg<"p11">;
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def P12 : PTXReg<"p12">;
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def P13 : PTXReg<"p13">;
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def P14 : PTXReg<"p14">;
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def P15 : PTXReg<"p15">;
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def P16 : PTXReg<"p16">;
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def P17 : PTXReg<"p17">;
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def P18 : PTXReg<"p18">;
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def P19 : PTXReg<"p19">;
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def P20 : PTXReg<"p20">;
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def P21 : PTXReg<"p21">;
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def P22 : PTXReg<"p22">;
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def P23 : PTXReg<"p23">;
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def P24 : PTXReg<"p24">;
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def P25 : PTXReg<"p25">;
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def P26 : PTXReg<"p26">;
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def P27 : PTXReg<"p27">;
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def P28 : PTXReg<"p28">;
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def P29 : PTXReg<"p29">;
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def P30 : PTXReg<"p30">;
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def P31 : PTXReg<"p31">;
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def P32 : PTXReg<"p32">;
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def P33 : PTXReg<"p33">;
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def P34 : PTXReg<"p34">;
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def P35 : PTXReg<"p35">;
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def P36 : PTXReg<"p36">;
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def P37 : PTXReg<"p37">;
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def P38 : PTXReg<"p38">;
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def P39 : PTXReg<"p39">;
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def P40 : PTXReg<"p40">;
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def P41 : PTXReg<"p41">;
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def P42 : PTXReg<"p42">;
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def P43 : PTXReg<"p43">;
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def P44 : PTXReg<"p44">;
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def P45 : PTXReg<"p45">;
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def P46 : PTXReg<"p46">;
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def P47 : PTXReg<"p47">;
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def P48 : PTXReg<"p48">;
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def P49 : PTXReg<"p49">;
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def P50 : PTXReg<"p50">;
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def P51 : PTXReg<"p51">;
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def P52 : PTXReg<"p52">;
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def P53 : PTXReg<"p53">;
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def P54 : PTXReg<"p54">;
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def P55 : PTXReg<"p55">;
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def P56 : PTXReg<"p56">;
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def P57 : PTXReg<"p57">;
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def P58 : PTXReg<"p58">;
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def P59 : PTXReg<"p59">;
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def P60 : PTXReg<"p60">;
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def P61 : PTXReg<"p61">;
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def P62 : PTXReg<"p62">;
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def P63 : PTXReg<"p63">;
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///===- 16-bit Integer Registers ------------------------------------------===//
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@ -96,63 +40,6 @@ def RH4 : PTXReg<"rh4">;
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def RH5 : PTXReg<"rh5">;
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def RH6 : PTXReg<"rh6">;
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def RH7 : PTXReg<"rh7">;
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def RH8 : PTXReg<"rh8">;
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def RH9 : PTXReg<"rh9">;
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def RH10 : PTXReg<"rh10">;
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def RH11 : PTXReg<"rh11">;
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def RH12 : PTXReg<"rh12">;
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def RH13 : PTXReg<"rh13">;
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def RH14 : PTXReg<"rh14">;
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def RH15 : PTXReg<"rh15">;
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def RH16 : PTXReg<"rh16">;
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def RH17 : PTXReg<"rh17">;
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def RH18 : PTXReg<"rh18">;
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def RH19 : PTXReg<"rh19">;
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def RH20 : PTXReg<"rh20">;
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def RH21 : PTXReg<"rh21">;
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def RH22 : PTXReg<"rh22">;
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def RH23 : PTXReg<"rh23">;
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def RH24 : PTXReg<"rh24">;
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def RH25 : PTXReg<"rh25">;
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def RH26 : PTXReg<"rh26">;
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def RH27 : PTXReg<"rh27">;
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def RH28 : PTXReg<"rh28">;
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def RH29 : PTXReg<"rh29">;
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def RH30 : PTXReg<"rh30">;
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def RH31 : PTXReg<"rh31">;
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def RH32 : PTXReg<"rh32">;
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def RH33 : PTXReg<"rh33">;
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def RH34 : PTXReg<"rh34">;
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def RH35 : PTXReg<"rh35">;
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def RH36 : PTXReg<"rh36">;
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def RH37 : PTXReg<"rh37">;
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def RH38 : PTXReg<"rh38">;
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def RH39 : PTXReg<"rh39">;
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def RH40 : PTXReg<"rh40">;
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def RH41 : PTXReg<"rh41">;
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def RH42 : PTXReg<"rh42">;
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def RH43 : PTXReg<"rh43">;
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def RH44 : PTXReg<"rh44">;
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def RH45 : PTXReg<"rh45">;
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def RH46 : PTXReg<"rh46">;
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def RH47 : PTXReg<"rh47">;
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def RH48 : PTXReg<"rh48">;
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def RH49 : PTXReg<"rh49">;
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def RH50 : PTXReg<"rh50">;
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def RH51 : PTXReg<"rh51">;
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def RH52 : PTXReg<"rh52">;
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def RH53 : PTXReg<"rh53">;
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def RH54 : PTXReg<"rh54">;
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def RH55 : PTXReg<"rh55">;
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def RH56 : PTXReg<"rh56">;
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def RH57 : PTXReg<"rh57">;
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def RH58 : PTXReg<"rh58">;
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def RH59 : PTXReg<"rh59">;
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def RH60 : PTXReg<"rh60">;
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def RH61 : PTXReg<"rh61">;
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def RH62 : PTXReg<"rh62">;
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def RH63 : PTXReg<"rh63">;
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///===- 32-bit Integer Registers ------------------------------------------===//
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@ -164,63 +51,6 @@ def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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def R8 : PTXReg<"r8">;
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def R9 : PTXReg<"r9">;
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def R10 : PTXReg<"r10">;
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def R11 : PTXReg<"r11">;
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def R12 : PTXReg<"r12">;
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def R13 : PTXReg<"r13">;
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def R14 : PTXReg<"r14">;
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def R15 : PTXReg<"r15">;
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def R16 : PTXReg<"r16">;
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def R17 : PTXReg<"r17">;
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def R18 : PTXReg<"r18">;
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def R19 : PTXReg<"r19">;
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def R20 : PTXReg<"r20">;
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def R21 : PTXReg<"r21">;
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def R22 : PTXReg<"r22">;
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def R23 : PTXReg<"r23">;
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def R24 : PTXReg<"r24">;
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def R25 : PTXReg<"r25">;
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def R26 : PTXReg<"r26">;
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def R27 : PTXReg<"r27">;
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def R28 : PTXReg<"r28">;
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def R29 : PTXReg<"r29">;
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def R30 : PTXReg<"r30">;
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def R31 : PTXReg<"r31">;
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def R32 : PTXReg<"r32">;
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def R33 : PTXReg<"r33">;
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def R34 : PTXReg<"r34">;
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def R35 : PTXReg<"r35">;
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def R36 : PTXReg<"r36">;
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def R37 : PTXReg<"r37">;
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def R38 : PTXReg<"r38">;
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def R39 : PTXReg<"r39">;
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def R40 : PTXReg<"r40">;
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def R41 : PTXReg<"r41">;
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def R42 : PTXReg<"r42">;
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def R43 : PTXReg<"r43">;
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def R44 : PTXReg<"r44">;
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def R45 : PTXReg<"r45">;
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def R46 : PTXReg<"r46">;
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def R47 : PTXReg<"r47">;
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def R48 : PTXReg<"r48">;
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def R49 : PTXReg<"r49">;
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def R50 : PTXReg<"r50">;
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def R51 : PTXReg<"r51">;
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def R52 : PTXReg<"r52">;
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def R53 : PTXReg<"r53">;
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def R54 : PTXReg<"r54">;
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def R55 : PTXReg<"r55">;
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def R56 : PTXReg<"r56">;
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def R57 : PTXReg<"r57">;
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def R58 : PTXReg<"r58">;
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def R59 : PTXReg<"r59">;
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def R60 : PTXReg<"r60">;
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def R61 : PTXReg<"r61">;
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def R62 : PTXReg<"r62">;
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def R63 : PTXReg<"r63">;
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///===- 64-bit Integer Registers ------------------------------------------===//
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@ -232,207 +62,14 @@ def RD4 : PTXReg<"rd4">;
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def RD5 : PTXReg<"rd5">;
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def RD6 : PTXReg<"rd6">;
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def RD7 : PTXReg<"rd7">;
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def RD8 : PTXReg<"rd8">;
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def RD9 : PTXReg<"rd9">;
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def RD10 : PTXReg<"rd10">;
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def RD11 : PTXReg<"rd11">;
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def RD12 : PTXReg<"rd12">;
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def RD13 : PTXReg<"rd13">;
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def RD14 : PTXReg<"rd14">;
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def RD15 : PTXReg<"rd15">;
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def RD16 : PTXReg<"rd16">;
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def RD17 : PTXReg<"rd17">;
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def RD18 : PTXReg<"rd18">;
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def RD19 : PTXReg<"rd19">;
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def RD20 : PTXReg<"rd20">;
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def RD21 : PTXReg<"rd21">;
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def RD22 : PTXReg<"rd22">;
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def RD23 : PTXReg<"rd23">;
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def RD24 : PTXReg<"rd24">;
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def RD25 : PTXReg<"rd25">;
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def RD26 : PTXReg<"rd26">;
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def RD27 : PTXReg<"rd27">;
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def RD28 : PTXReg<"rd28">;
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def RD29 : PTXReg<"rd29">;
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def RD30 : PTXReg<"rd30">;
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def RD31 : PTXReg<"rd31">;
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def RD32 : PTXReg<"rd32">;
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def RD33 : PTXReg<"rd33">;
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def RD34 : PTXReg<"rd34">;
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def RD35 : PTXReg<"rd35">;
|
||||
def RD36 : PTXReg<"rd36">;
|
||||
def RD37 : PTXReg<"rd37">;
|
||||
def RD38 : PTXReg<"rd38">;
|
||||
def RD39 : PTXReg<"rd39">;
|
||||
def RD40 : PTXReg<"rd40">;
|
||||
def RD41 : PTXReg<"rd41">;
|
||||
def RD42 : PTXReg<"rd42">;
|
||||
def RD43 : PTXReg<"rd43">;
|
||||
def RD44 : PTXReg<"rd44">;
|
||||
def RD45 : PTXReg<"rd45">;
|
||||
def RD46 : PTXReg<"rd46">;
|
||||
def RD47 : PTXReg<"rd47">;
|
||||
def RD48 : PTXReg<"rd48">;
|
||||
def RD49 : PTXReg<"rd49">;
|
||||
def RD50 : PTXReg<"rd50">;
|
||||
def RD51 : PTXReg<"rd51">;
|
||||
def RD52 : PTXReg<"rd52">;
|
||||
def RD53 : PTXReg<"rd53">;
|
||||
def RD54 : PTXReg<"rd54">;
|
||||
def RD55 : PTXReg<"rd55">;
|
||||
def RD56 : PTXReg<"rd56">;
|
||||
def RD57 : PTXReg<"rd57">;
|
||||
def RD58 : PTXReg<"rd58">;
|
||||
def RD59 : PTXReg<"rd59">;
|
||||
def RD60 : PTXReg<"rd60">;
|
||||
def RD61 : PTXReg<"rd61">;
|
||||
def RD62 : PTXReg<"rd62">;
|
||||
def RD63 : PTXReg<"rd63">;
|
||||
|
||||
|
||||
///===- 32-bit Floating-Point Registers -----------------------------------===//
|
||||
|
||||
def F0 : PTXReg<"f0">;
|
||||
def F1 : PTXReg<"f1">;
|
||||
def F2 : PTXReg<"f2">;
|
||||
def F3 : PTXReg<"f3">;
|
||||
def F4 : PTXReg<"f4">;
|
||||
def F5 : PTXReg<"f5">;
|
||||
def F6 : PTXReg<"f6">;
|
||||
def F7 : PTXReg<"f7">;
|
||||
def F8 : PTXReg<"f8">;
|
||||
def F9 : PTXReg<"f9">;
|
||||
def F10 : PTXReg<"f10">;
|
||||
def F11 : PTXReg<"f11">;
|
||||
def F12 : PTXReg<"f12">;
|
||||
def F13 : PTXReg<"f13">;
|
||||
def F14 : PTXReg<"f14">;
|
||||
def F15 : PTXReg<"f15">;
|
||||
def F16 : PTXReg<"f16">;
|
||||
def F17 : PTXReg<"f17">;
|
||||
def F18 : PTXReg<"f18">;
|
||||
def F19 : PTXReg<"f19">;
|
||||
def F20 : PTXReg<"f20">;
|
||||
def F21 : PTXReg<"f21">;
|
||||
def F22 : PTXReg<"f22">;
|
||||
def F23 : PTXReg<"f23">;
|
||||
def F24 : PTXReg<"f24">;
|
||||
def F25 : PTXReg<"f25">;
|
||||
def F26 : PTXReg<"f26">;
|
||||
def F27 : PTXReg<"f27">;
|
||||
def F28 : PTXReg<"f28">;
|
||||
def F29 : PTXReg<"f29">;
|
||||
def F30 : PTXReg<"f30">;
|
||||
def F31 : PTXReg<"f31">;
|
||||
def F32 : PTXReg<"f32">;
|
||||
def F33 : PTXReg<"f33">;
|
||||
def F34 : PTXReg<"f34">;
|
||||
def F35 : PTXReg<"f35">;
|
||||
def F36 : PTXReg<"f36">;
|
||||
def F37 : PTXReg<"f37">;
|
||||
def F38 : PTXReg<"f38">;
|
||||
def F39 : PTXReg<"f39">;
|
||||
def F40 : PTXReg<"f40">;
|
||||
def F41 : PTXReg<"f41">;
|
||||
def F42 : PTXReg<"f42">;
|
||||
def F43 : PTXReg<"f43">;
|
||||
def F44 : PTXReg<"f44">;
|
||||
def F45 : PTXReg<"f45">;
|
||||
def F46 : PTXReg<"f46">;
|
||||
def F47 : PTXReg<"f47">;
|
||||
def F48 : PTXReg<"f48">;
|
||||
def F49 : PTXReg<"f49">;
|
||||
def F50 : PTXReg<"f50">;
|
||||
def F51 : PTXReg<"f51">;
|
||||
def F52 : PTXReg<"f52">;
|
||||
def F53 : PTXReg<"f53">;
|
||||
def F54 : PTXReg<"f54">;
|
||||
def F55 : PTXReg<"f55">;
|
||||
def F56 : PTXReg<"f56">;
|
||||
def F57 : PTXReg<"f57">;
|
||||
def F58 : PTXReg<"f58">;
|
||||
def F59 : PTXReg<"f59">;
|
||||
def F60 : PTXReg<"f60">;
|
||||
def F61 : PTXReg<"f61">;
|
||||
def F62 : PTXReg<"f62">;
|
||||
def F63 : PTXReg<"f63">;
|
||||
|
||||
|
||||
///===- 64-bit Floating-Point Registers -----------------------------------===//
|
||||
|
||||
def FD0 : PTXReg<"fd0">;
|
||||
def FD1 : PTXReg<"fd1">;
|
||||
def FD2 : PTXReg<"fd2">;
|
||||
def FD3 : PTXReg<"fd3">;
|
||||
def FD4 : PTXReg<"fd4">;
|
||||
def FD5 : PTXReg<"fd5">;
|
||||
def FD6 : PTXReg<"fd6">;
|
||||
def FD7 : PTXReg<"fd7">;
|
||||
def FD8 : PTXReg<"fd8">;
|
||||
def FD9 : PTXReg<"fd9">;
|
||||
def FD10 : PTXReg<"fd10">;
|
||||
def FD11 : PTXReg<"fd11">;
|
||||
def FD12 : PTXReg<"fd12">;
|
||||
def FD13 : PTXReg<"fd13">;
|
||||
def FD14 : PTXReg<"fd14">;
|
||||
def FD15 : PTXReg<"fd15">;
|
||||
def FD16 : PTXReg<"fd16">;
|
||||
def FD17 : PTXReg<"fd17">;
|
||||
def FD18 : PTXReg<"fd18">;
|
||||
def FD19 : PTXReg<"fd19">;
|
||||
def FD20 : PTXReg<"fd20">;
|
||||
def FD21 : PTXReg<"fd21">;
|
||||
def FD22 : PTXReg<"fd22">;
|
||||
def FD23 : PTXReg<"fd23">;
|
||||
def FD24 : PTXReg<"fd24">;
|
||||
def FD25 : PTXReg<"fd25">;
|
||||
def FD26 : PTXReg<"fd26">;
|
||||
def FD27 : PTXReg<"fd27">;
|
||||
def FD28 : PTXReg<"fd28">;
|
||||
def FD29 : PTXReg<"fd29">;
|
||||
def FD30 : PTXReg<"fd30">;
|
||||
def FD31 : PTXReg<"fd31">;
|
||||
def FD32 : PTXReg<"fd32">;
|
||||
def FD33 : PTXReg<"fd33">;
|
||||
def FD34 : PTXReg<"fd34">;
|
||||
def FD35 : PTXReg<"fd35">;
|
||||
def FD36 : PTXReg<"fd36">;
|
||||
def FD37 : PTXReg<"fd37">;
|
||||
def FD38 : PTXReg<"fd38">;
|
||||
def FD39 : PTXReg<"fd39">;
|
||||
def FD40 : PTXReg<"fd40">;
|
||||
def FD41 : PTXReg<"fd41">;
|
||||
def FD42 : PTXReg<"fd42">;
|
||||
def FD43 : PTXReg<"fd43">;
|
||||
def FD44 : PTXReg<"fd44">;
|
||||
def FD45 : PTXReg<"fd45">;
|
||||
def FD46 : PTXReg<"f4d6">;
|
||||
def FD47 : PTXReg<"fd47">;
|
||||
def FD48 : PTXReg<"fd48">;
|
||||
def FD49 : PTXReg<"fd49">;
|
||||
def FD50 : PTXReg<"fd50">;
|
||||
def FD51 : PTXReg<"fd51">;
|
||||
def FD52 : PTXReg<"fd52">;
|
||||
def FD53 : PTXReg<"fd53">;
|
||||
def FD54 : PTXReg<"fd54">;
|
||||
def FD55 : PTXReg<"fd55">;
|
||||
def FD56 : PTXReg<"fd56">;
|
||||
def FD57 : PTXReg<"fd57">;
|
||||
def FD58 : PTXReg<"fd58">;
|
||||
def FD59 : PTXReg<"fd59">;
|
||||
def FD60 : PTXReg<"fd60">;
|
||||
def FD61 : PTXReg<"fd61">;
|
||||
def FD62 : PTXReg<"fd62">;
|
||||
def FD63 : PTXReg<"fd63">;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def Preds : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 63)>;
|
||||
def RRegu16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 63)>;
|
||||
def RRegu32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 63)>;
|
||||
def RRegu64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 63)>;
|
||||
def RRegf32 : RegisterClass<"PTX", [f32], 32, (sequence "F%u", 0, 63)>;
|
||||
def RRegf64 : RegisterClass<"PTX", [f64], 64, (sequence "FD%u", 0, 63)>;
|
||||
def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 7)>;
|
||||
def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 7)>;
|
||||
def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 7)>;
|
||||
def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 7)>;
|
||||
def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%u", 0, 7)>;
|
||||
def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%u", 0, 7)>;
|
||||
|
Loading…
Reference in New Issue
Block a user