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Drop the first argument of FPI, and asmprinterify fxch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15628 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -764,7 +764,7 @@ def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([m
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class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
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: X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
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class FPI<string n, bits<8> o, Format F, FPFormat fp> : FPInst<n, o, F, fp, NoMem, NoImm>;
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class FPI<bits<8> o, Format F, FPFormat fp> : FPInst<"", o, F, fp, NoMem, NoImm>;
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class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
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@ -777,14 +777,14 @@ class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem
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// because they can be expanded by the fp spackifier into one of many different
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// forms of instructions for doing these operations. Until the stackifier runs,
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// we prefer to be abstract.
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def FpMOV : FPI<"", 0, Pseudo, SpecialFP>; // f1 = fmov f2
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def FpADD : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
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def FpSUB : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
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def FpMUL : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
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def FpDIV : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
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def FpMOV : FPI<0, Pseudo, SpecialFP>; // f1 = fmov f2
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def FpADD : FPI<0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
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def FpSUB : FPI<0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
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def FpMUL : FPI<0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
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def FpDIV : FPI<0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
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def FpGETRESULT : FPI<"",0, Pseudo, SpecialFP>; // FPR = ST(0)
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def FpSETRESULT : FPI<"",0, Pseudo, SpecialFP>; // ST(0) = FPR
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def FpGETRESULT : FPI<0, Pseudo, SpecialFP>; // FPR = ST(0)
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def FpSETRESULT : FPI<0, Pseudo, SpecialFP>; // ST(0) = FPR
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// FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
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def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real]
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@ -827,22 +827,23 @@ def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int
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// Floating point cmovs...
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let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
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def FCMOVB : FPI<"" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
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def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
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II<(ops RST:$op), "fcmovb %ST(0), $op">;
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def FCMOVBE : FPI<"", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
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def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
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II<(ops RST:$op), "fcmovbe %ST(0), $op">;
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def FCMOVE : FPI<"" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
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def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
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II<(ops RST:$op), "fcmove %ST(0), $op">;
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def FCMOVAE : FPI<"", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
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def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
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II<(ops RST:$op), "fcmovae %ST(0), $op">;
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def FCMOVA : FPI<"" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
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def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
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II<(ops RST:$op), "fcmova %ST(0), $op">;
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def FCMOVNE : FPI<"", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
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def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
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II<(ops RST:$op), "fcmovne %ST(0), $op">;
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}
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// Floating point loads & stores...
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def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
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let Name = "fld" in
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def FLDrr : FPI<0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
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def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
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def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
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def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
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@ -850,8 +851,10 @@ def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load sign
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def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
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def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
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def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
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def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
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let Name = "fst" in
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def FSTrr : FPI<0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
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let Name = "fstp" in
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def FSTPrr : FPI<0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
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def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
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def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
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def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
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@ -864,20 +867,21 @@ def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store sig
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def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
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def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
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def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
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def FXCH : FPI<0xC8, AddRegFrm, NotFP>,
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II<(ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
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// Floating point constant loads...
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def FLD0 : FPI<"", 0xEE, RawFrm, ZeroArgFP>, D9,
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def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP>, D9,
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II<(ops), "fldz">;
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def FLD1 : FPI<"", 0xE8, RawFrm, ZeroArgFP>, D9,
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def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP>, D9,
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II<(ops), "fld1">;
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// Unary operations...
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def FCHS : FPI<"", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2
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II<(ops), "fchs">;
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def FTST : FPI<"", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0)
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II<(ops), "ftst">;
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def FCHS : FPI<0xE0, RawFrm, OneArgFPRW>, // f1 = fchs f2
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II<(ops), "fchs">, D9;
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def FTST : FPI<0xE4, RawFrm, OneArgFP>, // ftst ST(0)
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II<(ops), "ftst">, D9;
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// Binary arithmetic operations...
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class FPST0rInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, D8 {
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@ -916,15 +920,15 @@ def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), "fdivr $op, %ST(0)">; // ST(i
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def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop
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// Floating point compares
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def FUCOMr : FPI<"", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>, // FPSW = compare ST(0) with ST(i)
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II<(ops RST:$reg), "fucom $reg">;
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def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP>, // FPSW = compare ST(0) with ST(i)
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II<(ops RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>;
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def FUCOMPr : I<0xE8, AddRegFrm, (ops RST:$reg),
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"fucomp $reg">, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
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def FUCOMPPr : I<0xE9, RawFrm, (ops),
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"fucompp">, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
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def FUCOMIr : FPI<"", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i)
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II<(ops RST:$reg), "fucomi %ST(0), $reg">;
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def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP>, // CC = compare ST(0) with ST(i)
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II<(ops RST:$reg), "fucomi %ST(0), $reg">, DB, Imp<[ST0],[]>;
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def FUCOMIPr : I<0xE8, AddRegFrm, (ops RST:$reg),
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"fucomip %ST(0), $reg">, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop
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