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Fold (x & 8) != 0 and (x & 8) == 8 into (x & 8) >> 3.

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This turns this PPC code:

        rlwinm r2, r3, 0, 28, 28
        cmpwi cr7, r2, 8
        mfcr r2
        rlwinm r3, r2, 31, 31, 31

into this:

        rlwinm r2, r3, 0, 28, 28
        srwi r2, r2, 3
        rlwinm r3, r2, 0, 31, 31

Next up, nuking the extra and.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-21 06:12:41 +00:00
parent 956db27a63
commit 1c2a9b95dc
1 changed files with 22 additions and 0 deletions
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22
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -507,6 +507,28 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
// FIXME: Implement the rest of these.
// Fold bit comparisons when we can.
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
VT == N1.getValueType() && N1.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
return getNode(ISD::SRL, VT, N1,
getConstant(ExactLog2(AndRHS->getValue()),
TLI.getShiftAmountTy()));
}
} else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C2 is a single bit.
if ((C2 & (C2-1)) == 0) {
return getNode(ISD::SRL, VT, N1,
getConstant(ExactLog2(C2),TLI.getShiftAmountTy()));
}
}
}
}
} else if (isa<ConstantSDNode>(N1.Val)) {
// Ensure that the constant occurs on the RHS.