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* Commit the fix (by Chris) for a tblgen type inferencing bug.

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* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2005-12-04 08:18:16 +00:00
parent f8ac814957
commit 1c3d19eb15
4 changed files with 198 additions and 71 deletions
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utils/TableGen/CodeGenTarget.cpp
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@ -268,6 +268,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isTerminator = R->getValueAsBit("isTerminator");
hasDelaySlot = R->getValueAsBit("hasDelaySlot");
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
hasCtrlDep = R->getValueAsBit("hasCtrlDep");
hasVariableNumberOfOperands = false;
DagInit *DI;