6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-04 05:31:51 +00:00
Code Issues Projects Releases Wiki Activity

Rename variables to avoid confusion. No functionallity change intended.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-11-11 06:27:41 +00:00
parent a07d3fc693
commit 1c47de87c7
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/ARM/ARMFastISel.cpp
View File

@ -563,9 +563,9 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
// Use MVN to emit negative constants. // Use MVN to emit negative constants.
if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
unsigned Imm = (unsigned)~(CI->getSExtValue()); unsigned Imm = (unsigned)~(CI->getSExtValue());
bool EncodeImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
(ARM_AM::getSOImmVal(Imm) != -1); (ARM_AM::getSOImmVal(Imm) != -1);
if (EncodeImm) { if (UseImm) {
unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
@ -1232,25 +1232,25 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
// Check to see if the 2nd operand is a constant that we can encode directly // Check to see if the 2nd operand is a constant that we can encode directly
// in the compare. // in the compare.
int EncodedImm = 0; int Imm = 0;
bool EncodeImm = false; bool UseImm = false;
bool isNegativeImm = false; bool isNegativeImm = false;
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) { if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
SrcVT == MVT::i1) { SrcVT == MVT::i1) {
const APInt &CIVal = ConstInt->getValue(); const APInt &CIVal = ConstInt->getValue();
EncodedImm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue(); Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
if (EncodedImm < 0) { if (Imm < 0) {
isNegativeImm = true; isNegativeImm = true;
EncodedImm = -EncodedImm; Imm = -Imm;
} }
EncodeImm = isThumb2 ? (ARM_AM::getT2SOImmVal(EncodedImm) != -1) : UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
(ARM_AM::getSOImmVal(EncodedImm) != -1); (ARM_AM::getSOImmVal(Imm) != -1);
} }
} else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) { } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
if (SrcVT == MVT::f32 || SrcVT == MVT::f64) if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
if (ConstFP->isZero() && !ConstFP->isNegative()) if (ConstFP->isZero() && !ConstFP->isNegative())
EncodeImm = true; UseImm = true;
} }
unsigned CmpOpc; unsigned CmpOpc;
@ -1261,11 +1261,11 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
// TODO: Verify compares. // TODO: Verify compares.
case MVT::f32: case MVT::f32:
isICmp = false; isICmp = false;
CmpOpc = EncodeImm ? ARM::VCMPEZS : ARM::VCMPES; CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
break; break;
case MVT::f64: case MVT::f64:
isICmp = false; isICmp = false;
CmpOpc = EncodeImm ? ARM::VCMPEZD : ARM::VCMPED; CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
break; break;
case MVT::i1: case MVT::i1:
case MVT::i8: case MVT::i8:
@ -1274,12 +1274,12 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
// Intentional fall-through. // Intentional fall-through.
case MVT::i32: case MVT::i32:
if (isThumb2) { if (isThumb2) {
if (!EncodeImm) if (!UseImm)
CmpOpc = ARM::t2CMPrr; CmpOpc = ARM::t2CMPrr;
else else
CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri; CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri;
} else { } else {
if (!EncodeImm) if (!UseImm)
CmpOpc = ARM::CMPrr; CmpOpc = ARM::CMPrr;
else else
CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri; CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri;
@ -1291,7 +1291,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
if (SrcReg1 == 0) return false; if (SrcReg1 == 0) return false;
unsigned SrcReg2; unsigned SrcReg2;
if (!EncodeImm) { if (!UseImm) {
SrcReg2 = getRegForValue(Src2Value); SrcReg2 = getRegForValue(Src2Value);
if (SrcReg2 == 0) return false; if (SrcReg2 == 0) return false;
} }
@ -1302,14 +1302,14 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
if (ResultReg == 0) return false; if (ResultReg == 0) return false;
SrcReg1 = ResultReg; SrcReg1 = ResultReg;
if (!EncodeImm) { if (!UseImm) {
ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
if (ResultReg == 0) return false; if (ResultReg == 0) return false;
SrcReg2 = ResultReg; SrcReg2 = ResultReg;
} }
} }
if (!EncodeImm) { if (!UseImm) {
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(CmpOpc)) TII.get(CmpOpc))
.addReg(SrcReg1).addReg(SrcReg2)); .addReg(SrcReg1).addReg(SrcReg2));
@ -1320,7 +1320,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
// Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
if (isICmp) if (isICmp)
MIB.addImm(EncodedImm); MIB.addImm(Imm);
AddOptionalDefs(MIB); AddOptionalDefs(MIB);
} }