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Add a hacky workaround for crashes due to vectors live across blocks.

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Note that this code won't work for vectors that aren't legal on the
target.  Improvements coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26925 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-21 19:20:37 +00:00
parent c0a8b6df2a
commit 1c6191ffe7
3 changed files with 31 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -4262,6 +4262,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
/// type for the result.
SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
MVT::ValueType NewVT) {
// FIXME: THIS IS A TEMPORARY HACK
if (Op.getValueType() == NewVT) return Op;
assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
SDNode *Node = Op.Val;

3
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1086,7 +1086,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
break;
case ISD::BIT_CONVERT:
// Basic sanity checking.
assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())
assert((Operand.getValueType() == MVT::Vector || // FIXME: This is a hack.
MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()))
&& "Cannot BIT_CONVERT between two different types!");
if (VT == Operand.getValueType()) return Operand; // noop conversion.
if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)

26
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -2285,6 +2285,32 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
SelectionDAG &DAG = SDL.DAG;
if (SrcVT == DestVT) {
return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
} else if (SrcVT == MVT::Vector) {
// FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS!
// Figure out the right, legal destination reg to copy into.
const PackedType *PTy = cast<PackedType>(V->getType());
unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
unsigned NumVectorRegs = 1;
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
MVT::ValueType VT;
if (NumElts == 1)
VT = EltTy;
else
VT = getVectorType(EltTy, NumElts);
// FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL!
Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
} else if (SrcVT < DestVT) {
// The src value is promoted to the register.
if (MVT::isFloatingPoint(SrcVT))