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Add a hacky workaround for crashes due to vectors live across blocks.
Note that this code won't work for vectors that aren't legal on the target. Improvements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26925 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4262,6 +4262,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
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/// type for the result.
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SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
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MVT::ValueType NewVT) {
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// FIXME: THIS IS A TEMPORARY HACK
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if (Op.getValueType() == NewVT) return Op;
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assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
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SDNode *Node = Op.Val;
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@ -1086,7 +1086,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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break;
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case ISD::BIT_CONVERT:
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// Basic sanity checking.
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assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())
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assert((Operand.getValueType() == MVT::Vector || // FIXME: This is a hack.
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MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()))
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&& "Cannot BIT_CONVERT between two different types!");
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if (VT == Operand.getValueType()) return Operand; // noop conversion.
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if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
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@ -2285,6 +2285,32 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
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SelectionDAG &DAG = SDL.DAG;
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if (SrcVT == DestVT) {
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return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
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} else if (SrcVT == MVT::Vector) {
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// FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS!
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// Figure out the right, legal destination reg to copy into.
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const PackedType *PTy = cast<PackedType>(V->getType());
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unsigned NumElts = PTy->getNumElements();
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MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
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unsigned NumVectorRegs = 1;
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
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NumElts >>= 1;
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NumVectorRegs <<= 1;
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}
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MVT::ValueType VT;
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if (NumElts == 1)
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VT = EltTy;
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else
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VT = getVectorType(EltTy, NumElts);
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// FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL!
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Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
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return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
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} else if (SrcVT < DestVT) {
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// The src value is promoted to the register.
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if (MVT::isFloatingPoint(SrcVT))
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