mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Implemented Neon scalar by element intrinsics.
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ana Pazos
parent
42a9da35b8
commit
1c93766aa5
@ -196,9 +196,6 @@ def int_aarch64_neon_vaddds :
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def int_aarch64_neon_vadddu :
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Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
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// Scalar Saturating Add (Signed, Unsigned)
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def int_aarch64_neon_vqadds : Neon_2Arg_Intrinsic;
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def int_aarch64_neon_vqaddu : Neon_2Arg_Intrinsic;
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// Scalar Sub
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def int_aarch64_neon_vsubds :
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@ -206,9 +203,6 @@ def int_aarch64_neon_vsubds :
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def int_aarch64_neon_vsubdu :
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Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
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// Scalar Saturating Sub (Signed, Unsigned)
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def int_aarch64_neon_vqsubs : Neon_2Arg_Intrinsic;
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def int_aarch64_neon_vqsubu : Neon_2Arg_Intrinsic;
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// Scalar Shift
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// Scalar Shift Left
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@ -324,9 +318,6 @@ def int_aarch64_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
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// Signed Saturating Doubling Multiply-Subtract Long
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def int_aarch64_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
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// Signed Saturating Doubling Multiply Long
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def int_aarch64_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
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class Neon_2Arg_ShiftImm_Intrinsic
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: Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
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@ -4958,22 +4958,16 @@ defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
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defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
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defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Saturating Add, Sub (Signed, Unsigned)
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Saturating Add, Sub (Signed, Unsigned)
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
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SQADDhhh, SQADDsss, SQADDddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
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UQADDhhh, UQADDsss, UQADDddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
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SQSUBhhh, SQSUBsss, SQSUBddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
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UQSUBhhh, UQSUBsss, UQSUBddd>;
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// Scalar Integer Saturating Doubling Multiply Half High
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@ -5093,7 +5087,7 @@ defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
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// Signed Saturating Doubling Multiply Long
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defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
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defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
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defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
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SQDMULLshh, SQDMULLdss>;
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// Scalar Signed Integer Convert To Floating-point
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@ -5564,7 +5558,8 @@ multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
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OpNImm:$Imm))>;
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}
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// Scalar Floating Point fused multiply-add and multiply-subtract (scalar, by element)
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// Scalar Floating Point fused multiply-add and
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// multiply-subtract (scalar, by element)
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
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f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
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@ -5572,6 +5567,70 @@ defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
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f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
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// Scalar Signed saturating doubling multiply long (scalar, by element)
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def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
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let Inst{11} = 0b0; // h
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let Inst{21} = Imm{1}; // l
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let Inst{20} = Imm{0}; // m
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let Inst{19-16} = MRm{3-0};
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}
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def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
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let Inst{11} = Imm{2}; // h
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let Inst{21} = Imm{1}; // l
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let Inst{20} = Imm{0}; // m
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let Inst{19-16} = MRm{3-0};
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}
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def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
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let Inst{11} = 0b0; // h
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let Inst{21} = Imm{0}; // l
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let Inst{20-16} = MRm;
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}
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def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
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let Inst{11} = Imm{1}; // h
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let Inst{21} = Imm{0}; // l
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let Inst{20-16} = MRm;
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}
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multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
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SDPatternOperator opnode,
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Instruction INST,
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ValueType ResTy, RegisterClass FPRC,
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ValueType OpVTy, ValueType OpTy,
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ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
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def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
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(OpVTy (scalar_to_vector
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(ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
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(ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
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//swapped operands
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def : Pat<(ResTy (opnode
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(OpVTy (scalar_to_vector
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(ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
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(OpVTy FPRC:$Rn))),
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(ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
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}
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// Patterns for Scalar Signed saturating doubling
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// multiply long (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
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SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
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i32, VPR64Lo, neon_uimm2_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
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SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
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i32, VPR128Lo, neon_uimm3_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
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SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
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i32, VPR64Lo, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
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SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
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i32, VPR128Lo, neon_uimm2_bare>;
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// Scalar Signed saturating doubling multiply-add long (scalar, by element)
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def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
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0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
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@ -5629,34 +5688,64 @@ def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
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let Inst{20-16} = MRm;
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}
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// Scalar Signed saturating doubling multiply long (scalar, by element)
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def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
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let Inst{11} = 0b0; // h
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let Inst{21} = Imm{1}; // l
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let Inst{20} = Imm{0}; // m
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let Inst{19-16} = MRm{3-0};
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}
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def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
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let Inst{11} = Imm{2}; // h
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let Inst{21} = Imm{1}; // l
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let Inst{20} = Imm{0}; // m
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let Inst{19-16} = MRm{3-0};
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}
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def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
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let Inst{11} = 0b0; // h
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let Inst{21} = Imm{0}; // l
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let Inst{20-16} = MRm;
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}
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def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
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0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
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let Inst{11} = Imm{1}; // h
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let Inst{21} = Imm{0}; // l
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let Inst{20-16} = MRm;
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multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
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SDPatternOperator opnode,
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SDPatternOperator coreopnode,
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Instruction INST,
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ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
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ValueType OpTy,
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ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
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def : Pat<(ResTy (opnode
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(ResTy ResFPRC:$Ra),
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(ResTy (coreopnode (OpTy FPRC:$Rn),
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(OpTy (scalar_to_vector
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(ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
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(ResTy (INST (ResTy ResFPRC:$Ra),
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(OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
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// swapped operands
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def : Pat<(ResTy (opnode
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(ResTy ResFPRC:$Ra),
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(ResTy (coreopnode
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(OpTy (scalar_to_vector
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(ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
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(OpTy FPRC:$Rn))))),
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(ResTy (INST (ResTy ResFPRC:$Ra),
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(OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
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}
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// Patterns for Scalar Signed saturating
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// doubling multiply-add long (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
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int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
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i32, VPR64Lo, neon_uimm2_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
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int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
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i32, VPR128Lo, neon_uimm3_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
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int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
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i32, VPR64Lo, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
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int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
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i32, VPR128Lo, neon_uimm2_bare>;
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// Patterns for Scalar Signed saturating
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// doubling multiply-sub long (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
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int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
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i32, VPR64Lo, neon_uimm2_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
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int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
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i32, VPR128Lo, neon_uimm3_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
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int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
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i32, VPR64Lo, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
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int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
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i32, VPR128Lo, neon_uimm2_bare>;
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// Scalar Signed saturating doubling multiply returning
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// high half (scalar, by element)
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def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
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@ -5686,6 +5775,21 @@ def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
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let Inst{20-16} = MRm;
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}
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// Patterns for Scalar Signed saturating doubling multiply returning
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// high half (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
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SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
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i32, VPR64Lo, neon_uimm2_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
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SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
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i32, VPR128Lo, neon_uimm3_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
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SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
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i32, VPR64Lo, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
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SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
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i32, VPR128Lo, neon_uimm2_bare>;
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// Scalar Signed saturating rounding doubling multiply
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// returning high half (scalar, by element)
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def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
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@ -5715,6 +5819,18 @@ def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
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let Inst{20-16} = MRm;
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}
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
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SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
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VPR64Lo, neon_uimm2_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
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SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
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VPR128Lo, neon_uimm3_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
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SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
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VPR64Lo, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
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SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
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VPR128Lo, neon_uimm2_bare>;
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// Scalar Copy - DUP element to scalar
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class NeonI_Scalar_DUP<string asmop, string asmlane,
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@ -123,7 +123,7 @@ define i32 @test_vqdmullh_s16(i16 %a, i16 %b) {
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entry:
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%vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
|
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%vqdmull2.i = call <1 x i32> @llvm.arm.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
|
||||
%0 = extractelement <1 x i32> %vqdmull2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
@ -134,10 +134,10 @@ define i64 @test_vqdmulls_s32(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0
|
||||
%vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0
|
||||
%vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
|
||||
%vqdmull2.i = call <1 x i64> @llvm.arm.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
|
||||
%0 = extractelement <1 x i64> %vqdmull2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)
|
||||
|
||||
@ -1,171 +1,138 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
|
||||
declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
define <1 x i64> @test_uqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_uqadd_v1i64:
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
; CHECK: uqadd d0, d0, d1
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i64> @test_sqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_sqadd_v1i64:
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
; CHECK: sqadd d0, d0, d1
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
define <1 x i64> @test_uqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_uqsub_v1i64:
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
; CHECK: uqsub d0, d0, d1
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i64> @test_sqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_sqsub_v1i64:
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
; CHECK: sqsub d0, d0, d1
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i8> @llvm.aarch64.neon.vqaddu.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.aarch64.neon.vqadds.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8>, <1 x i8>)
|
||||
|
||||
define <1 x i8> @test_uqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
|
||||
; CHECK: test_uqadd_v1i8_aarch64:
|
||||
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
%tmp1 = call <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
;CHECK: uqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
|
||||
ret <1 x i8> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i8> @test_sqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
|
||||
; CHECK: test_sqadd_v1i8_aarch64:
|
||||
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
%tmp1 = call <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
;CHECK: sqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
|
||||
ret <1 x i8> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i8> @llvm.aarch64.neon.vqsubu.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.aarch64.neon.vqsubs.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8>, <1 x i8>)
|
||||
declare <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8>, <1 x i8>)
|
||||
|
||||
define <1 x i8> @test_uqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
|
||||
; CHECK: test_uqsub_v1i8_aarch64:
|
||||
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
;CHECK: uqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
|
||||
ret <1 x i8> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i8> @test_sqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
|
||||
; CHECK: test_sqsub_v1i8_aarch64:
|
||||
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
|
||||
;CHECK: sqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
|
||||
ret <1 x i8> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i16> @llvm.aarch64.neon.vqaddu.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.aarch64.neon.vqadds.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16>, <1 x i16>)
|
||||
|
||||
define <1 x i16> @test_uqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
|
||||
; CHECK: test_uqadd_v1i16_aarch64:
|
||||
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
%tmp1 = call <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
;CHECK: uqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
|
||||
ret <1 x i16> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i16> @test_sqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
|
||||
; CHECK: test_sqadd_v1i16_aarch64:
|
||||
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
%tmp1 = call <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
;CHECK: sqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
|
||||
ret <1 x i16> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i16> @llvm.aarch64.neon.vqsubu.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.aarch64.neon.vqsubs.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16>, <1 x i16>)
|
||||
|
||||
define <1 x i16> @test_uqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
|
||||
; CHECK: test_uqsub_v1i16_aarch64:
|
||||
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
;CHECK: uqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
|
||||
ret <1 x i16> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i16> @test_sqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
|
||||
; CHECK: test_sqsub_v1i16_aarch64:
|
||||
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
|
||||
;CHECK: sqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
|
||||
ret <1 x i16> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i32> @llvm.aarch64.neon.vqaddu.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vqadds.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32>, <1 x i32>)
|
||||
|
||||
define <1 x i32> @test_uqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
|
||||
; CHECK: test_uqadd_v1i32_aarch64:
|
||||
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
%tmp1 = call <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
;CHECK: uqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
|
||||
ret <1 x i32> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i32> @test_sqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
|
||||
; CHECK: test_sqadd_v1i32_aarch64:
|
||||
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
%tmp1 = call <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
;CHECK: sqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
|
||||
ret <1 x i32> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i32> @llvm.aarch64.neon.vqsubu.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vqsubs.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32>, <1 x i32>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32>, <1 x i32>)
|
||||
|
||||
define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
|
||||
; CHECK: test_uqsub_v1i32_aarch64:
|
||||
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
;CHECK: uqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
|
||||
ret <1 x i32> %tmp1
|
||||
}
|
||||
|
||||
|
||||
define <1 x i32> @test_sqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
|
||||
; CHECK: test_sqsub_v1i32_aarch64:
|
||||
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
|
||||
;CHECK: sqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
|
||||
ret <1 x i32> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i64> @llvm.aarch64.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
define <1 x i64> @test_uqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_uqadd_v1i64_aarch64:
|
||||
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
;CHECK: uqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i64> @test_sqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_sqadd_v1i64_aarch64:
|
||||
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
;CHECK: sqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
declare <1 x i64> @llvm.aarch64.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
define <1 x i64> @test_uqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_uqsub_v1i64_aarch64:
|
||||
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
;CHECK: uqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
|
||||
; CHECK: test_sqsub_v1i64_aarch64:
|
||||
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
|
||||
;CHECK: sqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
|
||||
ret <1 x i64> %tmp1
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user