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Do not use MachineOperand::isVirtualRegister either!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-10 21:12:22 +00:00
parent 9d58a500fc
commit 1cbe4d0ad0
7 changed files with 29 additions and 27 deletions
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3
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -115,7 +115,8 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
MachineOperand& mop = mi->getOperand(i);
if (mop.isVirtualRegister()) {
if (mop.isRegister() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
unsigned reg = mop.getAllocatedRegNum();
Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
assert(r2iit != r2iMap_.end());

14
lib/CodeGen/LiveVariables.cpp
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@ -231,11 +231,10 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isUse()) {
if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
if (MO.isUse() && MO.isRegister()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MO.isRegister() &&
MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
@ -250,16 +249,15 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isDef()) {
if (MO.isVirtualRegister()) {
if (MO.isDef() && MO.isRegister()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
VRInfo.DefBlock = MBB; // Created here...
VRInfo.DefInst = MI;
VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
} else if (MO.isRegister() &&
MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}

6
lib/CodeGen/PHIElimination.cpp
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@ -73,7 +73,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
// Unlink the PHI node from the basic block... but don't delete the PHI yet
MBB.erase(MBB.begin());
assert(MI->getOperand(0).isVirtualRegister() &&
assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
@ -174,7 +174,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
MachineInstr *PrevInst = *(I-1);
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
if (MO.isRegister() && MO.getReg() == IncomingReg)
if (MO.isDef()) {
HaveNotEmitted = false;
break;
@ -183,7 +183,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
}
if (HaveNotEmitted) { // If the copy has not already been emitted, do it.
assert(opVal.isVirtualRegister() &&
assert(MRegisterInfo::isVirtualRegister(opVal.getReg()) &&
"Machine PHI Operands must all be virtual registers!");
unsigned SrcReg = opVal.getReg();
RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);

10
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -116,12 +116,12 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
} else {
for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i) {
MachineOperand &MO = (*I)->getOperand(i);
assert(!MO.isVirtualRegister() &&
"Register allocation must be performed!");
if (MO.isRegister() && MO.isDef() &&
MRegisterInfo::isPhysicalRegister(MO.getReg()))
if (MO.isRegister() && MO.isDef()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Register allocation must be performed!");
ModifiedRegs[MO.getReg()] = true; // Register is modified
}
}
}
++I;
}

13
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -405,8 +405,9 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
i != e; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
if (op.isVirtualRegister()) {
unsigned virtReg = op.getAllocatedRegNum();
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getReg();
Virt2PhysMap::const_iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {
DEBUG(std::cerr << "\t\t\t%reg" << it->first
@ -441,7 +442,8 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
if (op.isVirtualRegister() && op.isUse()) {
if (op.isRegister() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
@ -471,9 +473,10 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
if (op.isVirtualRegister()) {
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
assert(!op.isUse() && "we should not have uses here!");
unsigned virtReg = op.getAllocatedRegNum();
unsigned virtReg = op.getReg();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {

8
lib/CodeGen/RegAllocLocal.cpp
View File

@ -522,8 +522,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isUse() &&
!MI->getOperand(i).isDef() &&
MI->getOperand(i).isVirtualRegister()){
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
@ -589,8 +589,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// we need to scavenge a register.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() &&
MI->getOperand(i).isVirtualRegister()) {
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
unsigned DestPhysReg;

2
lib/CodeGen/RegAllocSimple.cpp
View File

@ -174,7 +174,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
if (op.isVirtualRegister()) {
if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";