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Add simple reg-reg and reg-imm moves

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2009-07-16 13:29:38 +00:00
parent 87a24e3ee4
commit 1cc9dc7267
5 changed files with 80 additions and 8 deletions
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42
lib/Target/SystemZ/SystemZInstrInfo.cpp
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@@ -43,18 +43,46 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
}
bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
if (DestRC == SrcRC) {
unsigned Opc;
if (DestRC == &SystemZ::GR64RegClass) {
Opc = SystemZ::MOV64rr;
} else {
return false;
}
BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
return true;
}
return false;
}
bool
SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
return false;
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
switch (MI.getOpcode()) {
default:
return false;
case SystemZ::MOV64rr:
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid register-register move instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
}
bool