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Move subtarget dependent features into the subtarget from the target

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machine. Includes a fix for a subtarget initialization for
hard floating point on mips16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212240 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-07-03 00:10:24 +00:00
parent ba0f074283
commit 1ccffdf27f
4 changed files with 97 additions and 96 deletions
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76
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -114,18 +114,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
TSInfo(DL), JITInfo() {
if (InMips16Mode && !TM->Options.UseSoftFloat) {
// Hard float for mips16 means essentially to compile as soft float
// but to use a runtime library for soft float that is written with
// native mips32 floating point instructions (those runtime routines
// run in mips32 hard float mode).
TM->Options.UseSoftFloat = true;
TM->Options.FloatABIType = FloatABI::Soft;
InMips16HardFloat = true;
}
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)),
FrameLowering(MipsFrameLowering::create(*TM, *this)),
TLInfo(MipsTargetLowering::create(*TM)) {
PreviousInMips16Mode = InMips16Mode;
@ -189,14 +181,26 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
return OptLevel >= CodeGenOpt::Aggressive;
}
MipsSubtarget &MipsSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine *TM) {
std::string CPUName = selectMipsCPU(TargetTriple, CPU);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
if (InMips16Mode && !TM->Options.UseSoftFloat) {
// Hard float for mips16 means essentially to compile as soft float
// but to use a runtime library for soft float that is written with
// native mips32 floating point instructions (those runtime routines
// run in mips32 hard float mode).
TM->Options.UseSoftFloat = true;
TM->Options.FloatABIType = FloatABI::Soft;
InMips16HardFloat = true;
}
return *this;
}
@ -219,14 +223,14 @@ void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
return;
OverrideMode = Mips16Override;
PreviousInMips16Mode = true;
TM->setHelperClassesMips16();
setHelperClassesMips16();
return;
} else if (ChangeToNoMips16) {
if (!PreviousInMips16Mode)
return;
OverrideMode = NoMips16Override;
PreviousInMips16Mode = false;
TM->setHelperClassesMipsSE();
setHelperClassesMipsSE();
return;
} else {
if (OverrideMode == NoOverride)
@ -234,16 +238,52 @@ void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
OverrideMode = NoOverride;
DEBUG(dbgs() << "back to default" << "\n");
if (inMips16Mode() && !PreviousInMips16Mode) {
TM->setHelperClassesMips16();
setHelperClassesMips16();
PreviousInMips16Mode = true;
} else if (!inMips16Mode() && PreviousInMips16Mode) {
TM->setHelperClassesMipsSE();
setHelperClassesMipsSE();
PreviousInMips16Mode = false;
}
return;
}
}
void MipsSubtarget::setHelperClassesMips16() {
InstrInfoSE.swap(InstrInfo);
FrameLoweringSE.swap(FrameLowering);
TLInfoSE.swap(TLInfo);
if (!InstrInfo16) {
InstrInfo.reset(MipsInstrInfo::create(*TM));
FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
TLInfo.reset(MipsTargetLowering::create(*TM));
} else {
InstrInfo16.swap(InstrInfo);
FrameLowering16.swap(FrameLowering);
TLInfo16.swap(TLInfo);
}
assert(TLInfo && "null target lowering 16");
assert(InstrInfo && "null instr info 16");
assert(FrameLowering && "null frame lowering 16");
}
void MipsSubtarget::setHelperClassesMipsSE() {
InstrInfo16.swap(InstrInfo);
FrameLowering16.swap(FrameLowering);
TLInfo16.swap(TLInfo);
if (!InstrInfoSE) {
InstrInfo.reset(MipsInstrInfo::create(*TM));
FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
TLInfo.reset(MipsTargetLowering::create(*TM));
} else {
InstrInfoSE.swap(InstrInfo);
FrameLoweringSE.swap(FrameLowering);
TLInfoSE.swap(TLInfo);
}
assert(TLInfo && "null target lowering in SE");
assert(InstrInfo && "null instr info SE");
assert(FrameLowering && "null frame lowering SE");
}
bool MipsSubtarget::mipsSEUsesSoftFloat() const {
return TM->Options.UseSoftFloat && !InMips16HardFloat;
}

27
lib/Target/Mips/MipsSubtarget.h
View File

@ -14,6 +14,9 @@
#ifndef MIPSSUBTARGET_H
#define MIPSSUBTARGET_H
#include "MipsFrameLowering.h"
#include "MipsISelLowering.h"
#include "MipsInstrInfo.h"
#include "MipsJITInfo.h"
#include "MipsSelectionDAGInfo.h"
#include "llvm/IR/DataLayout.h"
@ -139,6 +142,15 @@ protected:
const DataLayout DL; // Calculates type size & alignment
const MipsSelectionDAGInfo TSInfo;
MipsJITInfo JITInfo;
std::unique_ptr<const MipsInstrInfo> InstrInfo;
std::unique_ptr<const MipsFrameLowering> FrameLowering;
std::unique_ptr<const MipsTargetLowering> TLInfo;
std::unique_ptr<const MipsInstrInfo> InstrInfo16;
std::unique_ptr<const MipsFrameLowering> FrameLowering16;
std::unique_ptr<const MipsTargetLowering> TLInfo16;
std::unique_ptr<const MipsInstrInfo> InstrInfoSE;
std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
std::unique_ptr<const MipsTargetLowering> TLInfoSE;
public:
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
@ -250,7 +262,8 @@ public:
/// \brief Reset the subtarget for the Mips target.
void resetSubtarget(MachineFunction *MF);
MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine *TM);
/// Does the system support unaligned memory access.
///
@ -259,9 +272,21 @@ public:
/// hybrid implementations are all valid.
bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
// Set helper classes
void setHelperClassesMips16();
void setHelperClassesMipsSE();
MipsJITInfo *getJITInfo() { return &JITInfo; }
const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
const DataLayout *getDataLayout() const { return &DL; }
const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
const TargetFrameLowering *getFrameLowering() const {
return FrameLowering.get();
}
const MipsRegisterInfo *getRegisterInfo() const {
return &InstrInfo->getRegisterInfo();
}
const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); }
};
} // End llvm namespace

41
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -56,49 +56,10 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, isLittle, RM, this),
InstrInfo(MipsInstrInfo::create(*this)),
FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
TLInfo(MipsTargetLowering::create(*this)) {
Subtarget(TT, CPU, FS, isLittle, RM, this) {
initAsmInfo();
}
void MipsTargetMachine::setHelperClassesMips16() {
InstrInfoSE.swap(InstrInfo);
FrameLoweringSE.swap(FrameLowering);
TLInfoSE.swap(TLInfo);
if (!InstrInfo16) {
InstrInfo.reset(MipsInstrInfo::create(*this));
FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
TLInfo.reset(MipsTargetLowering::create(*this));
} else {
InstrInfo16.swap(InstrInfo);
FrameLowering16.swap(FrameLowering);
TLInfo16.swap(TLInfo);
}
assert(TLInfo && "null target lowering 16");
assert(InstrInfo && "null instr info 16");
assert(FrameLowering && "null frame lowering 16");
}
void MipsTargetMachine::setHelperClassesMipsSE() {
InstrInfo16.swap(InstrInfo);
FrameLowering16.swap(FrameLowering);
TLInfo16.swap(TLInfo);
if (!InstrInfoSE) {
InstrInfo.reset(MipsInstrInfo::create(*this));
FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
TLInfo.reset(MipsTargetLowering::create(*this));
} else {
InstrInfoSE.swap(InstrInfo);
FrameLoweringSE.swap(FrameLowering);
TLInfoSE.swap(TLInfo);
}
assert(TLInfo && "null target lowering in SE");
assert(InstrInfo && "null instr info SE");
assert(FrameLowering && "null frame lowering SE");
}
void MipsebTargetMachine::anchor() { }
MipsebTargetMachine::

49
lib/Target/Mips/MipsTargetMachine.h
View File

@ -14,9 +14,6 @@
#ifndef MIPSTARGETMACHINE_H
#define MIPSTARGETMACHINE_H
#include "MipsFrameLowering.h"
#include "MipsISelLowering.h"
#include "MipsInstrInfo.h"
#include "MipsSubtarget.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
@ -29,52 +26,37 @@ class MipsRegisterInfo;
class MipsTargetMachine : public LLVMTargetMachine {
MipsSubtarget Subtarget;
std::unique_ptr<const MipsInstrInfo> InstrInfo;
std::unique_ptr<const MipsFrameLowering> FrameLowering;
std::unique_ptr<const MipsTargetLowering> TLInfo;
std::unique_ptr<const MipsInstrInfo> InstrInfo16;
std::unique_ptr<const MipsFrameLowering> FrameLowering16;
std::unique_ptr<const MipsTargetLowering> TLInfo16;
std::unique_ptr<const MipsInstrInfo> InstrInfoSE;
std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
std::unique_ptr<const MipsTargetLowering> TLInfoSE;
public:
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
virtual ~MipsTargetMachine() {}
void addAnalysisPasses(PassManagerBase &PM) override;
const MipsInstrInfo *getInstrInfo() const override
{ return InstrInfo.get(); }
const TargetFrameLowering *getFrameLowering() const override
{ return FrameLowering.get(); }
const MipsSubtarget *getSubtargetImpl() const override
{ return &Subtarget; }
const MipsInstrInfo *getInstrInfo() const override {
return getSubtargetImpl()->getInstrInfo();
}
const TargetFrameLowering *getFrameLowering() const override {
return getSubtargetImpl()->getFrameLowering();
}
const MipsSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const InstrItineraryData *getInstrItineraryData() const override {
return Subtarget.inMips16Mode()
? nullptr
: &getSubtargetImpl()->getInstrItineraryData();
}
MipsJITInfo *getJITInfo() override {
return Subtarget.getJITInfo();
}
const MipsRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo();
return getSubtargetImpl()->getRegisterInfo();
}
const MipsTargetLowering *getTargetLowering() const override {
return TLInfo.get();
return getSubtargetImpl()->getTargetLowering();
}
const DataLayout *getDataLayout() const override {
return getSubtargetImpl()->getDataLayout();
}
@ -85,13 +67,6 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
// Set helper classes
void setHelperClassesMips16();
void setHelperClassesMipsSE();
};
/// MipsebTargetMachine - Mips32/64 big endian target machine.