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https://github.com/c64scene-ar/llvm-6502.git
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Factor out x86 segment override prefix encoding, and also use it for VEX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -129,10 +129,14 @@ public:
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const;
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void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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raw_ostream &OS) const;
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void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const;
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@ -356,8 +360,9 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
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/// called VEX.
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void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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int MemOperand, const MCInst &MI,
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const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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bool HasVEX_4V = false;
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if ((TSFlags >> 32) & X86II::VEX_4V)
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HasVEX_4V = true;
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@ -509,6 +514,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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assert(0 && "Not implemented!");
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}
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// Emit segment override opcode prefix as needed.
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EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
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// VEX opcode prefix can have 2 or 3 bytes
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//
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// 3 bytes:
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@ -628,20 +636,11 @@ static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
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return REX;
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}
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/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
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///
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/// MemOperand is the operand # of the start of a memory operand if present. If
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/// Not present, it is -1.
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void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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const TargetInstrDesc &Desc,
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/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
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void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
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unsigned &CurByte, int MemOperand,
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const MCInst &MI,
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raw_ostream &OS) const {
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// Emit the lock opcode prefix as needed.
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if (TSFlags & X86II::LOCK)
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EmitByte(0xF0, CurByte, OS);
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// Emit segment override opcode prefix as needed.
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switch (TSFlags & X86II::SegOvrMask) {
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default: assert(0 && "Invalid segment!");
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case 0:
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@ -666,6 +665,23 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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EmitByte(0x65, CurByte, OS);
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break;
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}
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}
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/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
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///
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/// MemOperand is the operand # of the start of a memory operand if present. If
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/// Not present, it is -1.
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void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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// Emit the lock opcode prefix as needed.
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if (TSFlags & X86II::LOCK)
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EmitByte(0xF0, CurByte, OS);
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// Emit segment override opcode prefix as needed.
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EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
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// Emit the repeat opcode prefix as needed.
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if ((TSFlags & X86II::Op0Mask) == X86II::REP)
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@ -776,8 +792,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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if (!HasVEXPrefix)
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EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
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else
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// FIXME: Segment overrides??
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EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
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EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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unsigned SrcRegNum = 0;
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