mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-18 12:31:26 +00:00
[SystemZ] Use MVC to spill loads and stores
Try to use MVC when spilling the destination of a simple load or the source
of a simple store. As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet. spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.
I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...
Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
9188443a2d
commit
1ce4894a3f
@ -13,6 +13,7 @@
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#include "SystemZInstrInfo.h"
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#include "SystemZInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_INSTRINFO_CTOR
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@ -80,7 +81,8 @@ void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
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// Return 0 otherwise.
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//
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// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
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static int isSimpleMove(const MachineInstr *MI, int &FrameIndex, int Flag) {
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static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
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unsigned Flag) {
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const MCInstrDesc &MCID = MI->getDesc();
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if ((MCID.TSFlags & Flag) &&
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MI->getOperand(1).isFI() &&
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@ -315,6 +317,96 @@ SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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FrameIdx);
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}
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// Return true if MI is a simple load or store with a 12-bit displacement
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// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
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static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
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const MCInstrDesc &MCID = MI->getDesc();
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return ((MCID.TSFlags & Flag) &&
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isUInt<12>(MI->getOperand(2).getImm()) &&
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MI->getOperand(3).getReg() == 0);
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}
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// Return a MachineMemOperand for FrameIndex with flags MMOFlags.
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// Offset is the byte offset from the start of FrameIndex.
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static MachineMemOperand *getFrameMMO(MachineFunction &MF, int FrameIndex,
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uint64_t &Offset, unsigned MMOFlags) {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const Value *V = PseudoSourceValue::getFixedStack(FrameIndex);
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return MF.getMachineMemOperand(MachinePointerInfo(V, Offset), MMOFlags,
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MFI->getObjectSize(FrameIndex),
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MFI->getObjectAlignment(FrameIndex));
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}
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MachineInstr *
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SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned Size = MFI->getObjectSize(FrameIndex);
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// Eary exit for cases we don't care about
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if (Ops.size() != 1)
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return 0;
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unsigned OpNum = Ops[0];
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unsigned Reg = MI->getOperand(OpNum).getReg();
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unsigned RegSize = MF.getRegInfo().getRegClass(Reg)->getSize();
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assert(Size == RegSize && "Invalid size combination");
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// Look for cases where the source of a simple store or the destination
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// of a simple load is being spilled. Try to use MVC instead.
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//
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// Although MVC is in practice a fast choice in these cases, it is still
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// logically a bytewise copy. This means that we cannot use it if the
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// load or store is volatile. It also means that the transformation is
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// not valid in cases where the two memories partially overlap; however,
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// that is not a problem here, because we know that one of the memories
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// is a full frame index.
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//
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// For now we punt if the load or store is also to a frame index.
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// In that case we might end up eliminating both of them to out-of-range
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// offsets, which might then force the register scavenger to spill two
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// other registers. The backend can only handle one such scavenger spill
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// at a time.
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if (OpNum == 0 && MI->hasOneMemOperand()) {
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MachineMemOperand *MMO = *MI->memoperands_begin();
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if (MMO->getSize() == Size && !MMO->isVolatile()) {
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// Handle conversion of loads.
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if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad) &&
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!MI->getOperand(1).isFI()) {
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uint64_t Offset = 0;
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MachineMemOperand *FrameMMO = getFrameMMO(MF, FrameIndex, Offset,
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MachineMemOperand::MOStore);
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return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
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.addFrameIndex(FrameIndex).addImm(Offset).addImm(Size)
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.addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
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.addMemOperand(FrameMMO).addMemOperand(MMO);
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}
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// Handle conversion of stores.
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if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore) &&
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!MI->getOperand(1).isFI()) {
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uint64_t Offset = 0;
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MachineMemOperand *FrameMMO = getFrameMMO(MF, FrameIndex, Offset,
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MachineMemOperand::MOLoad);
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return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
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.addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
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.addImm(Size).addFrameIndex(FrameIndex).addImm(Offset)
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.addMemOperand(MMO).addMemOperand(FrameMMO);
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}
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}
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}
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return 0;
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}
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MachineInstr *
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SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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bool
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SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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switch (MI->getOpcode()) {
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@ -111,6 +111,14 @@ public:
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
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virtual MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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virtual bool
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expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
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virtual bool
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@ -242,11 +242,8 @@ let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
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// Register loads.
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let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
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defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
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def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
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def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
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def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
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defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
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def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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@ -255,16 +252,16 @@ let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
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[(set GR128:$dst, (load bdxaddr20only128:$src))]>;
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}
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}
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let canFoldAsLoad = 1 in {
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def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
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def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
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}
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// Register stores.
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let SimpleBDXStore = 1 in {
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let isCodeGenOnly = 1 in {
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defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
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def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
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}
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def STG : StoreRXY<"stg", 0xE324, store, GR64>;
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def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
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let isCodeGenOnly = 1 in
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defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
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def STG : StoreRXY<"stg", 0xE324, store, GR64>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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@ -273,6 +270,9 @@ let SimpleBDXStore = 1 in {
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[(store GR128:$src, bdxaddr20only128:$dst)]>;
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}
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}
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let isCodeGenOnly = 1 in
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def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
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def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
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// 8-bit immediate stores to 8-bit fields.
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defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
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40
test/CodeGen/SystemZ/Large/spill-01.py
Normal file
40
test/CodeGen/SystemZ/Large/spill-01.py
Normal file
@ -0,0 +1,40 @@
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# Test cases where MVC is used for spill slots that end up being out of range.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
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# There are 8 usable call-saved GPRs, two of which are needed for the base
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# registers. The first 160 bytes of the frame are needed for the ABI
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# call frame, and a further 8 bytes are needed for the emergency spill slot.
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# That means we will have at least one out-of-range slot if:
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#
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# count == (4096 - 168) / 8 + 6 + 1 == 498
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#
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# Add in some extra room and check both %r15+4096 (the first out-of-range slot)
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# and %r15+4104.
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#
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# CHECK: f1:
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# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
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# CHECK: mvc 0(8,[[REG]]), {{[0-9]+}}({{%r[0-9]+}})
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# CHECK: brasl %r14, foo@PLT
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# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
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# CHECK: mvc {{[0-9]+}}(8,{{%r[0-9]+}}), 8([[REG]])
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# CHECK: br %r14
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count = 500
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print 'declare void @foo()'
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print ''
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print 'define void @f1(i64 *%base0, i64 *%base1) {'
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for i in range(count):
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print ' %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
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print ' %%val%d = load i64 *%%ptr%d' % (i, i)
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print ''
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print ' call void @foo()'
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print ''
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for i in range(count):
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print ' store i64 %%val%d, i64 *%%ptr%d' % (i, i)
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print ''
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print ' ret void'
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print '}'
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46
test/CodeGen/SystemZ/Large/spill-02.py
Normal file
46
test/CodeGen/SystemZ/Large/spill-02.py
Normal file
@ -0,0 +1,46 @@
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# Test cases where we spill from one frame index to another, both of which
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# would be out of range of MVC. At present we don't use MVC in this case.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
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# There are 8 usable call-saved GPRs. The first 160 bytes of the frame
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# are needed for the ABI call frame, and a further 8 bytes are needed
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# for the emergency spill slot. That means we will have at least one
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# out-of-range slot if:
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#
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# count == (4096 - 168) / 8 + 8 + 1 == 500
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#
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# Add in some extra just to be sure.
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#
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# CHECK: f1:
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# CHECK-NOT: mvc
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# CHECK: br %r14
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count = 510
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print 'declare void @foo(i64 *%base0, i64 *%base1)'
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print ''
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print 'define void @f1() {'
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for i in range(2):
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print ' %%alloc%d = alloca [%d x i64]' % (i, count / 2)
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print (' %%base%d = getelementptr [%d x i64] * %%alloc%d, i64 0, i64 0'
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% (i, count / 2, i))
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print ' call void @foo(i64 *%base0, i64 *%base1)'
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print ''
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for i in range(count):
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print ' %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
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print ' %%val%d = load i64 *%%ptr%d' % (i, i)
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print ''
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print ' call void @foo(i64 *%base0, i64 *%base1)'
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print ''
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for i in range (count):
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print ' store i64 %%val%d, i64 *%%ptr%d' % (i, i)
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print ''
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print ' call void @foo(i64 *%base0, i64 *%base1)'
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print ''
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print ' ret void'
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print '}'
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383
test/CodeGen/SystemZ/spill-01.ll
Normal file
383
test/CodeGen/SystemZ/spill-01.ll
Normal file
@ -0,0 +1,383 @@
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; Test spilling using MVC.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @foo()
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@g0 = global i32 0
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@g1 = global i32 1
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@g2 = global i32 2
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@g3 = global i32 3
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@g4 = global i32 4
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@g5 = global i32 5
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@g6 = global i32 6
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@g7 = global i32 7
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@g8 = global i32 8
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@g9 = global i32 9
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@h0 = global i64 0
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@h1 = global i64 1
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@h2 = global i64 2
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@h3 = global i64 3
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@h4 = global i64 4
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@h5 = global i64 5
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@h6 = global i64 6
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@h7 = global i64 7
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@h8 = global i64 8
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@h9 = global i64 9
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; This function shouldn't spill anything
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define void @f1(i32 *%ptr0) {
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; CHECK: f1:
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; CHECK: stmg
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; CHECK: aghi %r15, -160
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; CHECK-NOT: %r15
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: lmg
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; CHECK: br %r14
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%ptr1 = getelementptr i32 *%ptr0, i32 2
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%ptr2 = getelementptr i32 *%ptr0, i32 4
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%ptr3 = getelementptr i32 *%ptr0, i32 6
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%ptr4 = getelementptr i32 *%ptr0, i32 8
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%ptr5 = getelementptr i32 *%ptr0, i32 10
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%ptr6 = getelementptr i32 *%ptr0, i32 12
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%val0 = load i32 *%ptr0
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%val1 = load i32 *%ptr1
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%val2 = load i32 *%ptr2
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%val3 = load i32 *%ptr3
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%val4 = load i32 *%ptr4
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%val5 = load i32 *%ptr5
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%val6 = load i32 *%ptr6
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call void @foo()
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store i32 %val0, i32 *%ptr0
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store i32 %val1, i32 *%ptr1
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store i32 %val2, i32 *%ptr2
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store i32 %val3, i32 *%ptr3
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store i32 %val4, i32 *%ptr4
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store i32 %val5, i32 *%ptr5
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store i32 %val6, i32 *%ptr6
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ret void
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}
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; Test a case where at least one i32 load and at least one i32 store
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; need spills.
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define void @f2(i32 *%ptr0) {
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; CHECK: f2:
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; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
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; CHECK: brasl %r14, foo@PLT
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; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32 *%ptr0, i64 16
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%val0 = load i32 *%ptr0
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%val1 = load i32 *%ptr1
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%val2 = load i32 *%ptr2
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%val3 = load i32 *%ptr3
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%val4 = load i32 *%ptr4
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%val5 = load i32 *%ptr5
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%val6 = load i32 *%ptr6
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%val7 = load i32 *%ptr7
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%val8 = load i32 *%ptr8
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call void @foo()
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store i32 %val0, i32 *%ptr0
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store i32 %val1, i32 *%ptr1
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store i32 %val2, i32 *%ptr2
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store i32 %val3, i32 *%ptr3
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store i32 %val4, i32 *%ptr4
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store i32 %val5, i32 *%ptr5
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store i32 %val6, i32 *%ptr6
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store i32 %val7, i32 *%ptr7
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store i32 %val8, i32 *%ptr8
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ret void
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}
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; Test a case where at least one i64 load and at least one i64 store
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; need spills.
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define void @f3(i64 *%ptr0) {
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; CHECK: f3:
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; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
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; CHECK: brasl %r14, foo@PLT
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; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i64 *%ptr0, i64 2
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%ptr2 = getelementptr i64 *%ptr0, i64 4
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%ptr3 = getelementptr i64 *%ptr0, i64 6
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%ptr4 = getelementptr i64 *%ptr0, i64 8
|
||||
%ptr5 = getelementptr i64 *%ptr0, i64 10
|
||||
%ptr6 = getelementptr i64 *%ptr0, i64 12
|
||||
%ptr7 = getelementptr i64 *%ptr0, i64 14
|
||||
%ptr8 = getelementptr i64 *%ptr0, i64 16
|
||||
|
||||
%val0 = load i64 *%ptr0
|
||||
%val1 = load i64 *%ptr1
|
||||
%val2 = load i64 *%ptr2
|
||||
%val3 = load i64 *%ptr3
|
||||
%val4 = load i64 *%ptr4
|
||||
%val5 = load i64 *%ptr5
|
||||
%val6 = load i64 *%ptr6
|
||||
%val7 = load i64 *%ptr7
|
||||
%val8 = load i64 *%ptr8
|
||||
|
||||
call void @foo()
|
||||
|
||||
store i64 %val0, i64 *%ptr0
|
||||
store i64 %val1, i64 *%ptr1
|
||||
store i64 %val2, i64 *%ptr2
|
||||
store i64 %val3, i64 *%ptr3
|
||||
store i64 %val4, i64 *%ptr4
|
||||
store i64 %val5, i64 *%ptr5
|
||||
store i64 %val6, i64 *%ptr6
|
||||
store i64 %val7, i64 *%ptr7
|
||||
store i64 %val8, i64 *%ptr8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Test a case where at least at least one f32 load and at least one f32 store
|
||||
; need spills. The 8 call-saved FPRs could be used for 8 of the %vals
|
||||
; (and are at the time of writing), but it would really be better to use
|
||||
; MVC for all 10.
|
||||
define void @f4(float *%ptr0) {
|
||||
; CHECK: f4:
|
||||
; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
|
||||
; CHECK: br %r14
|
||||
%ptr1 = getelementptr float *%ptr0, i64 2
|
||||
%ptr2 = getelementptr float *%ptr0, i64 4
|
||||
%ptr3 = getelementptr float *%ptr0, i64 6
|
||||
%ptr4 = getelementptr float *%ptr0, i64 8
|
||||
%ptr5 = getelementptr float *%ptr0, i64 10
|
||||
%ptr6 = getelementptr float *%ptr0, i64 12
|
||||
%ptr7 = getelementptr float *%ptr0, i64 14
|
||||
%ptr8 = getelementptr float *%ptr0, i64 16
|
||||
%ptr9 = getelementptr float *%ptr0, i64 18
|
||||
|
||||
%val0 = load float *%ptr0
|
||||
%val1 = load float *%ptr1
|
||||
%val2 = load float *%ptr2
|
||||
%val3 = load float *%ptr3
|
||||
%val4 = load float *%ptr4
|
||||
%val5 = load float *%ptr5
|
||||
%val6 = load float *%ptr6
|
||||
%val7 = load float *%ptr7
|
||||
%val8 = load float *%ptr8
|
||||
%val9 = load float *%ptr9
|
||||
|
||||
call void @foo()
|
||||
|
||||
store float %val0, float *%ptr0
|
||||
store float %val1, float *%ptr1
|
||||
store float %val2, float *%ptr2
|
||||
store float %val3, float *%ptr3
|
||||
store float %val4, float *%ptr4
|
||||
store float %val5, float *%ptr5
|
||||
store float %val6, float *%ptr6
|
||||
store float %val7, float *%ptr7
|
||||
store float %val8, float *%ptr8
|
||||
store float %val9, float *%ptr9
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Similarly for f64.
|
||||
define void @f5(double *%ptr0) {
|
||||
; CHECK: f5:
|
||||
; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
|
||||
; CHECK: br %r14
|
||||
%ptr1 = getelementptr double *%ptr0, i64 2
|
||||
%ptr2 = getelementptr double *%ptr0, i64 4
|
||||
%ptr3 = getelementptr double *%ptr0, i64 6
|
||||
%ptr4 = getelementptr double *%ptr0, i64 8
|
||||
%ptr5 = getelementptr double *%ptr0, i64 10
|
||||
%ptr6 = getelementptr double *%ptr0, i64 12
|
||||
%ptr7 = getelementptr double *%ptr0, i64 14
|
||||
%ptr8 = getelementptr double *%ptr0, i64 16
|
||||
%ptr9 = getelementptr double *%ptr0, i64 18
|
||||
|
||||
%val0 = load double *%ptr0
|
||||
%val1 = load double *%ptr1
|
||||
%val2 = load double *%ptr2
|
||||
%val3 = load double *%ptr3
|
||||
%val4 = load double *%ptr4
|
||||
%val5 = load double *%ptr5
|
||||
%val6 = load double *%ptr6
|
||||
%val7 = load double *%ptr7
|
||||
%val8 = load double *%ptr8
|
||||
%val9 = load double *%ptr9
|
||||
|
||||
call void @foo()
|
||||
|
||||
store double %val0, double *%ptr0
|
||||
store double %val1, double *%ptr1
|
||||
store double %val2, double *%ptr2
|
||||
store double %val3, double *%ptr3
|
||||
store double %val4, double *%ptr4
|
||||
store double %val5, double *%ptr5
|
||||
store double %val6, double *%ptr6
|
||||
store double %val7, double *%ptr7
|
||||
store double %val8, double *%ptr8
|
||||
store double %val9, double *%ptr9
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Repeat f2 with atomic accesses. We shouldn't use MVC here.
|
||||
define void @f6(i32 *%ptr0) {
|
||||
; CHECK: f6:
|
||||
; CHECK-NOT: mvc
|
||||
; CHECK: br %r14
|
||||
%ptr1 = getelementptr i32 *%ptr0, i64 2
|
||||
%ptr2 = getelementptr i32 *%ptr0, i64 4
|
||||
%ptr3 = getelementptr i32 *%ptr0, i64 6
|
||||
%ptr4 = getelementptr i32 *%ptr0, i64 8
|
||||
%ptr5 = getelementptr i32 *%ptr0, i64 10
|
||||
%ptr6 = getelementptr i32 *%ptr0, i64 12
|
||||
%ptr7 = getelementptr i32 *%ptr0, i64 14
|
||||
%ptr8 = getelementptr i32 *%ptr0, i64 16
|
||||
|
||||
%val0 = load atomic i32 *%ptr0 unordered, align 4
|
||||
%val1 = load atomic i32 *%ptr1 unordered, align 4
|
||||
%val2 = load atomic i32 *%ptr2 unordered, align 4
|
||||
%val3 = load atomic i32 *%ptr3 unordered, align 4
|
||||
%val4 = load atomic i32 *%ptr4 unordered, align 4
|
||||
%val5 = load atomic i32 *%ptr5 unordered, align 4
|
||||
%val6 = load atomic i32 *%ptr6 unordered, align 4
|
||||
%val7 = load atomic i32 *%ptr7 unordered, align 4
|
||||
%val8 = load atomic i32 *%ptr8 unordered, align 4
|
||||
|
||||
call void @foo()
|
||||
|
||||
store atomic i32 %val0, i32 *%ptr0 unordered, align 4
|
||||
store atomic i32 %val1, i32 *%ptr1 unordered, align 4
|
||||
store atomic i32 %val2, i32 *%ptr2 unordered, align 4
|
||||
store atomic i32 %val3, i32 *%ptr3 unordered, align 4
|
||||
store atomic i32 %val4, i32 *%ptr4 unordered, align 4
|
||||
store atomic i32 %val5, i32 *%ptr5 unordered, align 4
|
||||
store atomic i32 %val6, i32 *%ptr6 unordered, align 4
|
||||
store atomic i32 %val7, i32 *%ptr7 unordered, align 4
|
||||
store atomic i32 %val8, i32 *%ptr8 unordered, align 4
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...likewise volatile accesses.
|
||||
define void @f7(i32 *%ptr0) {
|
||||
; CHECK: f7:
|
||||
; CHECK-NOT: mvc
|
||||
; CHECK: br %r14
|
||||
%ptr1 = getelementptr i32 *%ptr0, i64 2
|
||||
%ptr2 = getelementptr i32 *%ptr0, i64 4
|
||||
%ptr3 = getelementptr i32 *%ptr0, i64 6
|
||||
%ptr4 = getelementptr i32 *%ptr0, i64 8
|
||||
%ptr5 = getelementptr i32 *%ptr0, i64 10
|
||||
%ptr6 = getelementptr i32 *%ptr0, i64 12
|
||||
%ptr7 = getelementptr i32 *%ptr0, i64 14
|
||||
%ptr8 = getelementptr i32 *%ptr0, i64 16
|
||||
|
||||
%val0 = load volatile i32 *%ptr0
|
||||
%val1 = load volatile i32 *%ptr1
|
||||
%val2 = load volatile i32 *%ptr2
|
||||
%val3 = load volatile i32 *%ptr3
|
||||
%val4 = load volatile i32 *%ptr4
|
||||
%val5 = load volatile i32 *%ptr5
|
||||
%val6 = load volatile i32 *%ptr6
|
||||
%val7 = load volatile i32 *%ptr7
|
||||
%val8 = load volatile i32 *%ptr8
|
||||
|
||||
call void @foo()
|
||||
|
||||
store volatile i32 %val0, i32 *%ptr0
|
||||
store volatile i32 %val1, i32 *%ptr1
|
||||
store volatile i32 %val2, i32 *%ptr2
|
||||
store volatile i32 %val3, i32 *%ptr3
|
||||
store volatile i32 %val4, i32 *%ptr4
|
||||
store volatile i32 %val5, i32 *%ptr5
|
||||
store volatile i32 %val6, i32 *%ptr6
|
||||
store volatile i32 %val7, i32 *%ptr7
|
||||
store volatile i32 %val8, i32 *%ptr8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that LRL and STRL are not converted.
|
||||
define void @f8() {
|
||||
; CHECK: f8:
|
||||
; CHECK-NOT: mvc
|
||||
; CHECK: br %r14
|
||||
%val0 = load i32 *@g0
|
||||
%val1 = load i32 *@g1
|
||||
%val2 = load i32 *@g2
|
||||
%val3 = load i32 *@g3
|
||||
%val4 = load i32 *@g4
|
||||
%val5 = load i32 *@g5
|
||||
%val6 = load i32 *@g6
|
||||
%val7 = load i32 *@g7
|
||||
%val8 = load i32 *@g8
|
||||
%val9 = load i32 *@g9
|
||||
|
||||
call void @foo()
|
||||
|
||||
store i32 %val0, i32 *@g0
|
||||
store i32 %val1, i32 *@g1
|
||||
store i32 %val2, i32 *@g2
|
||||
store i32 %val3, i32 *@g3
|
||||
store i32 %val4, i32 *@g4
|
||||
store i32 %val5, i32 *@g5
|
||||
store i32 %val6, i32 *@g6
|
||||
store i32 %val7, i32 *@g7
|
||||
store i32 %val8, i32 *@g8
|
||||
store i32 %val9, i32 *@g9
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Likewise LGRL and STGRL.
|
||||
define void @f9() {
|
||||
; CHECK: f9:
|
||||
; CHECK-NOT: mvc
|
||||
; CHECK: br %r14
|
||||
%val0 = load i64 *@h0
|
||||
%val1 = load i64 *@h1
|
||||
%val2 = load i64 *@h2
|
||||
%val3 = load i64 *@h3
|
||||
%val4 = load i64 *@h4
|
||||
%val5 = load i64 *@h5
|
||||
%val6 = load i64 *@h6
|
||||
%val7 = load i64 *@h7
|
||||
%val8 = load i64 *@h8
|
||||
%val9 = load i64 *@h9
|
||||
|
||||
call void @foo()
|
||||
|
||||
store i64 %val0, i64 *@h0
|
||||
store i64 %val1, i64 *@h1
|
||||
store i64 %val2, i64 *@h2
|
||||
store i64 %val3, i64 *@h3
|
||||
store i64 %val4, i64 *@h4
|
||||
store i64 %val5, i64 *@h5
|
||||
store i64 %val6, i64 *@h6
|
||||
store i64 %val7, i64 *@h7
|
||||
store i64 %val8, i64 *@h8
|
||||
store i64 %val9, i64 *@h9
|
||||
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user