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Add support for the 'c' constraint.
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2999,13 +2999,15 @@ getConstraintType(const std::string &Constraint) const
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// unless generating MIPS16 code.
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// 'y' : Equivalent to r; retained for
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// backwards compatibility.
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// 'f' : Floating Point registers.
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// 'c' : A register suitable for use in an indirect
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// jump. This will always be $25 for -mabicalls.
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default : break;
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case 'd':
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case 'y':
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case 'f':
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case 'c':
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return C_RegisterClass;
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}
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}
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@ -3039,6 +3041,10 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
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if (type->isFloatTy())
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weight = CW_Register;
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break;
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case 'c': // $25 for indirect jumps
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if (type->isIntegerTy())
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weight = CW_SpecificReg;
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break;
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case 'I': // signed 16 bit immediate
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case 'J': // integer zero
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case 'K': // unsigned 16 bit immediate
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@ -3078,6 +3084,12 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
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return std::make_pair(0U, &Mips::FGR64RegClass);
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return std::make_pair(0U, &Mips::AFGR64RegClass);
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}
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break;
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case 'c': // register suitable for indirect jump
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if (VT == MVT::i32)
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return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
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assert(VT == MVT::i64 && "Unexpected type.");
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return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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@ -23,5 +23,11 @@ entry:
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;CHECK: #NO_APP
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tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
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; Now c with 1024: make sure register $25 is picked
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; CHECK: #APP
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; CHECK: addi $25,${{[0-9]+}},1024
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
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ret i32 0
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}
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