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SparcV9 doesnt have rem instruction either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1341,6 +1341,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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// ... nor does SparcV9.
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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}
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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23
test/CodeGen/SPARC/rem.ll
Normal file
23
test/CodeGen/SPARC/rem.ll
Normal file
@ -0,0 +1,23 @@
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; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK-LABEL: test1:
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; CHECK: sdivx %o0, %o1, %o2
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; CHECK-NEXT: mulx %o2, %o1, %o1
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; CHECK-NEXT: jmp %o7+8
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; CHECK-NEXT: sub %o0, %o1, %o0
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define i64 @test1(i64 %X, i64 %Y) {
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%tmp1 = srem i64 %X, %Y
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ret i64 %tmp1
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}
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; CHECK-LABEL: test2:
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; CHECK: udivx %o0, %o1, %o2
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; CHECK-NEXT: mulx %o2, %o1, %o1
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; CHECK-NEXT: jmp %o7+8
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; CHECK-NEXT: sub %o0, %o1, %o0
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define i64 @test2(i64 %X, i64 %Y) {
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%tmp1 = urem i64 %X, %Y
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ret i64 %tmp1
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}
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