6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-23 17:29:19 +00:00
Code Issues Projects Releases Wiki Activity

SparcV9 doesnt have rem instruction either.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Divacky 2013-10-31 19:22:33 +00:00
parent 844e7d35d4
commit 1d6d49fbb1
2 changed files with 31 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1341,6 +1341,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// ... nor does SparcV9.
if (Subtarget->is64Bit()) {
setOperationAction(ISD::UREM, MVT::i64, Expand);
setOperationAction(ISD::SREM, MVT::i64, Expand);
setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
}
// Custom expand fp<->sint
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);

23
test/CodeGen/SPARC/rem.ll Normal file
View File

@ -0,0 +1,23 @@
; RUN: llc < %s -march=sparcv9 | FileCheck %s
; CHECK-LABEL: test1:
; CHECK: sdivx %o0, %o1, %o2
; CHECK-NEXT: mulx %o2, %o1, %o1
; CHECK-NEXT: jmp %o7+8
; CHECK-NEXT: sub %o0, %o1, %o0
define i64 @test1(i64 %X, i64 %Y) {
%tmp1 = srem i64 %X, %Y
ret i64 %tmp1
}
; CHECK-LABEL: test2:
; CHECK: udivx %o0, %o1, %o2
; CHECK-NEXT: mulx %o2, %o1, %o1
; CHECK-NEXT: jmp %o7+8
; CHECK-NEXT: sub %o0, %o1, %o0
define i64 @test2(i64 %X, i64 %Y) {
%tmp1 = urem i64 %X, %Y
ret i64 %tmp1
}