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Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
bits in a word). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -411,3 +411,4 @@ include "llvm/IntrinsicsX86.td"
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include "llvm/IntrinsicsARM.td"
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include "llvm/IntrinsicsARM.td"
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include "llvm/IntrinsicsCellSPU.td"
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include "llvm/IntrinsicsCellSPU.td"
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include "llvm/IntrinsicsAlpha.td"
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include "llvm/IntrinsicsAlpha.td"
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include "llvm/IntrinsicsXCore.td"
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14
include/llvm/IntrinsicsXCore.td
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14
include/llvm/IntrinsicsXCore.td
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@ -0,0 +1,14 @@
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//==- IntrinsicsXCore.td - XCore intrinsics -*- tablegen -*-==//
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//
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// Copyright (C) 2008 XMOS
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the XCore-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
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def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
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def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
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}
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@ -226,9 +226,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
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}
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}
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static inline SDValue BuildGetId(SelectionDAG &DAG) {
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static inline SDValue BuildGetId(SelectionDAG &DAG) {
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// TODO
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
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assert(0 && "Unimplemented");
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DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
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return SDValue();
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}
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}
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static inline bool isZeroLengthArray(const Type *Ty) {
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static inline bool isZeroLengthArray(const Type *Ty) {
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@ -750,7 +750,7 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
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// getd, testlcl, tinitlr, getps, setps
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// getd, testlcl, tinitlr, getps, setps
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def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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"bitrev $dst, $src",
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"bitrev $dst, $src",
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[]>;
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[(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
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def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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"byterev $dst, $src",
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"byterev $dst, $src",
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@ -790,7 +790,7 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
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let Defs = [R11] in
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let Defs = [R11] in
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def GETID_0R : _F0R<(outs), (ins),
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def GETID_0R : _F0R<(outs), (ins),
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"get r11, id",
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"get r11, id",
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[]>;
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[(set R11, (int_xcore_getid))]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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// Non-Instruction Patterns
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8
test/CodeGen/XCore/bitrev.ll
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8
test/CodeGen/XCore/bitrev.ll
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@ -0,0 +1,8 @@
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; RUN: llvm-as < %s | llc -march=xcore > %t1.s
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; RUN: grep bitrev %t1.s | count 1
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declare i32 @llvm.xcore.bitrev(i32)
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define i32 @test(i32 %val) {
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%result = call i32 @llvm.xcore.bitrev(i32 %val)
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ret i32 %result
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}
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8
test/CodeGen/XCore/getid.ll
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8
test/CodeGen/XCore/getid.ll
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; RUN: llvm-as < %s | llc -march=xcore > %t1.s
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; RUN: grep "get r11, id" %t1.s | count 1
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declare i32 @llvm.xcore.getid()
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define i32 @test() {
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%result = call i32 @llvm.xcore.getid()
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ret i32 %result
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}
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