6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-24 23:29:41 +00:00
Code Issues Projects Releases Wiki Activity

Add XCore intrinsics for getid (returns thread id) and bitrev (reverses

Browse Source 
bits in a word).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2008-11-14 10:12:16 +00:00
parent 56c523c63b
commit 1d8f975890
6 changed files with 35 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/llvm/Intrinsics.td
View File

@ -411,3 +411,4 @@ include "llvm/IntrinsicsX86.td"
include "llvm/IntrinsicsARM.td"
include "llvm/IntrinsicsCellSPU.td"
include "llvm/IntrinsicsAlpha.td"
include "llvm/IntrinsicsXCore.td"

14
include/llvm/IntrinsicsXCore.td Normal file
View File

@ -0,0 +1,14 @@
//==- IntrinsicsXCore.td - XCore intrinsics -*- tablegen -*-==//
//
// Copyright (C) 2008 XMOS
//
//===----------------------------------------------------------------------===//
//
// This file defines all of the XCore-specific intrinsics.
//
//===----------------------------------------------------------------------===//
let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
}

5
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -226,9 +226,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
}
static inline SDValue BuildGetId(SelectionDAG &DAG) {
// TODO
assert(0 && "Unimplemented");
return SDValue();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
}
static inline bool isZeroLengthArray(const Type *Ty) {

4
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -750,7 +750,7 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
// getd, testlcl, tinitlr, getps, setps
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"bitrev $dst, $src",
[]>;
[(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"byterev $dst, $src",
@ -790,7 +790,7 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
let Defs = [R11] in
def GETID_0R : _F0R<(outs), (ins),
"get r11, id",
[]>;
[(set R11, (int_xcore_getid))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns

8
test/CodeGen/XCore/bitrev.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; RUN: grep bitrev %t1.s | count 1
declare i32 @llvm.xcore.bitrev(i32)
define i32 @test(i32 %val) {
%result = call i32 @llvm.xcore.bitrev(i32 %val)
ret i32 %result
}

8
test/CodeGen/XCore/getid.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; RUN: grep "get r11, id" %t1.s | count 1
declare i32 @llvm.xcore.getid()
define i32 @test() {
%result = call i32 @llvm.xcore.getid()
ret i32 %result
}