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X86 itinerary properties.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-06-05 03:44:46 +00:00
parent f94f051cf5
commit 1d98530196
2 changed files with 29 additions and 2 deletions
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24
lib/Target/X86/X86Schedule.td
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@ -456,6 +456,28 @@ def IIC_NOP : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
def GenericItineraries : ProcessorItineraries<[], [], []>;
// IssueWidth is analagous to the number of decode units. Core and its
// descendents, including Nehalem and SandyBridge have 4 decoders.
// Resources beyond the decoder operate on micro-ops and are bufferred
// so adjacent micro-ops don't directly compete.
//
// MinLatency=0 indicates that RAW dependencies can be decoded in the
// same cycle.
//
// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
// indicates high latency opcodes. Alternatively, InstrItinData
// entries may be included here to define specific operand
// latencies. Since these latencies are not used for pipeline hazards,
// they do not need to be exact.
//
// This set of instruction itineraries should contain no reference to
// InstrStages. When an iterary has no stages, the scheduler can
// bypass the logic needed for checking pipeline stage hazards.
def GenericItineraries : MultiIssueItineraries<
4, // IssueWidth
0, // MinLatency
4, // LoadLatency (expected, may be overriden by OperandCycles)
10, // HighLatency (expected, may be overriden by OperandCycles)
[], [], []>; // no FuncUnits, Bypasses, or InstrItinData.
include "X86ScheduleAtom.td"

7
lib/Target/X86/X86ScheduleAtom.td
View File

@ -22,7 +22,12 @@ def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
// SIMD/FP: SIMD ALU, FP Adder
def AtomItineraries : ProcessorItineraries<
def AtomItineraries : MultiIssueItineraries<
2, // IssueWidth=2 allows 2 instructions per scheduling group.
1, // MinLatency=1. InstrStage cycles overrides MinLatency.
// OperandCycles may be used for expected latency.
3, // LoadLatency (expected, may be overriden by OperandCycles)
30,// HighLatency (expected, may be overriden by OperandCycles)
[ Port0, Port1 ],
[], [
// P0 only